74SSTUA32866BFG8 IDT, Integrated Device Technology Inc, 74SSTUA32866BFG8 Datasheet - Page 7

• Manufacturer Part Number: 74SSTUA32866BFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTUA32866BFG8

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 2.4ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

FUNCTION TABLE
NOTES:
1. H = HIGH Voltage Level
2. Output level before the indicated steady-state conditions were established.
PARITY AND STANDBY FUNCTION TABLE
NOTES:
1. H = HIGH Voltage Level
2. Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
3. PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
4. This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
is driven LOW.
RESET
RESET
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
X or Floating
X or Floating
DCS
DCS
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
X or Floating
X or Floating
CSR
CSR
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
(EACH FLIP-FLOP) (1)
X or Floating
X or Floating
Inputs
L or H
L or H
L or H
L or H
L or H
CLK
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Inputs
X or Floating
X or Floating
L or H
L or H
L or H
L or H
L or H
CLK
CLK
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Σ Σ Σ Σ Σ of Inputs = H (D1 - D25)
7
Dx, DODT, DCKE
(1)
X or Floating
X or Floating
Even
Even
Even
Even
Odd
Odd
Odd
Odd
H
H
H
H
L
X
L
X
L
X
L
X
X
X
X or Floating
PAR_IN
Outputs
COMMERCIAL TEMPERATURE RANGE
Q
Q
Q
Q
Q
Q
Qx
H
H
H
L
0
L
0
L
0
0
0
0
L
H
H
H
H
X
X
L
L
L
L
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Output
QCSx
Q
Q
Q
Q
PPO
H
H
H
H
PPO
PPO
L
L
L
L
L
0
0
0
0
(2)
(2)
(2)
(2)
H
H
H
H
L
L
L
L
L
(3)
0
0
Outputs
QODTx, QCKEx
Outputs
QERR
QERR
QERR
Q
Q
Q
Q
H
H
H
H
L
0
L
0
L
0
L
0
L
(2)
(2)
(2)
(2)
H
H
H
H
H
L
L
L
L
(4)
0
0