SSTUA32S869BHLFT IDT, Integrated Device Technology Inc, SSTUA32S869BHLFT Datasheet - Page 3

• Manufacturer Part Number: SSTUA32S869BHLFT
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUA32S869BHLFT

• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 28
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 340(Min)MHz
• Mounting: Surface Mount
• Pin Count: 150
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Parity and Standby Function Table
1173—10/28/05
RESET#
NOTE 1
NOTE 3 This transition assumes PTYERR1# is high at the crossing of CK going high and CK# going low.
NOTE 2
H
H
H
H
H
H
H
H
H
H
L
Inputs D1, D4 and D4 are not included in this range.
PARIN1 arrives one (C1 = 0) or two (C = 1) clock cycles after data to which it applies.
If PTYERR1# is low, it stays latched low for two clock cycles or until RESET# is driven low. PARIN1 is
used to generate PPO1 and PTYERR1#.
floating
DCS#
X or
H
L
L
L
L
L
L
L
L
X
floating
CSR#
X or
H
X
X
X
X
X
L
L
L
L
floating
L or H
X or
CK
↑
↑
↑
↑
↑
↑
↑
↑
↑
Inputs
floating
L or H
CK#
X or
↓
↓
↓
↓
↓
↓
↓
↓
↓
£ of inputs = H
3
D1..… D14
floating
Even
Even
Even
Even
Odd
Odd
Odd
Odd
X or
X
X
(1)
Advance Information
PARIN1
floating
ICSSSTUA32S869B
X or
H
H
H
H
X
X
L
L
L
L
(2)
PPO1
PPOn
PPOn
H
H
H
H
L
L
L
L
L
(2)
0
0
Output
PTYERR1#
PTYERRn
PTYERRn
H
H
H
H
H
L
L
L
L
0
0
(3)
#
#