74SSTU32864CBFG IDT, Integrated Device Technology Inc, 74SSTU32864CBFG Datasheet - Page 9
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
74SSTU32864CBFG
Manufacturer Part Number
74SSTU32864CBFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.74SSTU32864CBFG.pdf
(12 pages)
Specifications of 74SSTU32864CBFG
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Package Type
LFBGA
Propagation Delay Time
2.35ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
340(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74SSTU32864CBFG
Manufacturer:
IDT
Quantity:
22 000
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
NOTES:
1. 270MHz max clock frequency for parts assembled and tested prior to WW37.
2. Data and V
3. Data, V
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS.
2. Includes 350ps of test load transmission line delay.
3. This parameter is not production tested.
4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
IDT74SSTU32864/A/C/D/G
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
Symbol
f
CLOCK
t
INACT (3)
t
ACT (2)
t
dV/dt_Δ
t
Symbol
PDMSS
tw
SU
t
dV/dt_r
H
dV/dt_f
t
PDM
t
f
RPHL
MAX
(1)
(2)
REF
(2,3)
(4)
, and clock inputs must be held at valid levels (not floating) a minimum time of t
REF
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup Time
Hold Time
inputs must be low a minimum time of t
Parameter
CLK and CLK to Q
CLK and CLK to Q (simultaneous switching)
RESET to Q
Output slew rate from 20% to 80%
Output slew rate from 20% to 80%
Output slew rate from 20% to 80%
DCS before CLK↑, CLK↓, CSR HIGH
DCS before CLK↑, CLK↓, CSR LOW
DODT, CSR, Data, and DCKE before CLK↑, CLK↓
Data, DCS, CSR, DCKE, and DODT after CLK↑, CLK↓
ACT
max, after RESET is taken HIGH.
9
(1)
1.41
Min
340
—
—
—
1
1
INACT
max, after RESET is taken LOW.
V
DD
= 1.8V ± 0.1V
Min.
0.7
0.5
0.5
0.5
—
—
—
1
V
DD
= 1.8V ± 0.1V
Max.
2.15
2.35
—
3
4
4
1
COMMERCIAL TEMPERATURE RANGE
Max.
340
—
10
15
—
—
—
—
MHz
V/ns
V/ns
V/ns
Unit
ns
ns
ns
MHz
Unit
ns
ns
ns
ns
ns