MT41J256M4HX-187E:D TR Micron Technology Inc, MT41J256M4HX-187E:D TR Datasheet - Page 14
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MT41J256M4HX-187E:D TR
Manufacturer Part Number
MT41J256M4HX-187E:D TR
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J256M4HX-187ED_TR.pdf
(208 pages)
Specifications of MT41J256M4HX-187E:D TR
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
190mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Functional Block Diagrams
Figure 3: 256 Meg x 4 Functional Block Diagram
RZQ
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
V
SSQ
A[13:0]
BA[2:0]
CK, CK#
ZQ
RESET#
RAS#
CAS#
ODT
WE#
CKE
A12
CS#
17
Address
register
Mode registers
Control
logic
16
counter
Refresh
14
ZQCL, ZQCS
11
3
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
BC4 (burst chop)
OTF
14
address
3
Row-
MUX
Column-
counter/
address
control
14
Bank
logic
latch
ZQ CAL
decoder
address
Bank 0
row-
latch
and
Bank 1
Bank 2
8
3
Bank 3
Bank 4
16,384
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 7
(16,384 x 256 x 32)
To pull-up/pull-down
Sense amplifiers
DM mask logic
I/O gating
decoder
memory
Column
Bank 0
(x32)
array
8,192
networks
256
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
14
Bank 6
Bank 7
DM
32
BC4
OTF
Micron Technology, Inc. reserves the right to change products or specifications without notice.
32
32
Columns 0, 1, and 2
interface
CK, CK#
READ
MUX
FIFO
data
and
Data
1Gb: x4, x8, x16 DDR3 SDRAM
Data
4
4
lower nibble for BC4)
Functional Block Diagrams
(select upper or
Column 2
WRITE
drivers
input
logic
and
control
CK, CK#
ODT
drivers
READ
BC4
DLL
© 2006 Micron Technology, Inc. All rights reserved.
DQS, DQS#
DQ[3:0]
sw1
sw1
sw1
R
R
R
V
V
V
TT,nom
TT,nom
TT,nom
DDQ
DDQ
DDQ
/2
/2
/2
R
R
R
sw2
sw2
TT(WR)
sw2
TT(WR)
TT(WR)
(1, 2)
(1 . . . 4)
DQ[3:0]
DQS, DQS#
DM
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