MT41J256M4HX-187E:D TR Micron Technology Inc, MT41J256M4HX-187E:D TR Datasheet - Page 191
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MT41J256M4HX-187E:D TR
Manufacturer Part Number
MT41J256M4HX-187E:D TR
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J256M4HX-187ED_TR.pdf
(208 pages)
Specifications of MT41J256M4HX-187E:D TR
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
190mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
DQS, DQS#
Figure 111: Dynamic ODT: Without WRITE Command
DQS, DQS#
Command
Command
Address
Address
ODT
CK#
DQ
R
CK
ODT
TT
CK#
DQ
R
CK
TT
NOP
T0
Valid
T0
NOP
T1
Valid
T1
Notes:
Notes:
NOP
T2
ODTL on
ODTH4
Valid
NOP
T3
T2
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
1. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
ODTL on
registered LOW at T5 is also legal.
t AON (MIN)
t AON (MAX)
WRS4
Valid
T4
ODTH4
Valid
T3
t AON (MIN)
t AON (MAX)
NOP
T5
ODTL
Valid
R
cnw
TT,nom
T4
ODTH4
NOP
T6
TT,nom
WL
Valid
NOP
T7
is enabled and R
T5
ODTL
cwn
t ADC (MIN)
t ADC (MAX)
NOP
4
T8
Valid
T6
TT,nom
NOP
T9
DI
n
R
TT(WR)
TT(WR)
and R
n + 1
DI
Valid
T7
NOP
T10
n + 2
DI
R
TT(WR)
is either enabled or disabled.
TT,nom
n + 3
DI
Valid
NOP
T11
are enabled.
T8
ODTL off
t ADC (MIN)
t ADC (MAX)
T12
NOP
t AOF (MIN)
Valid
T9
t AOF (MAX)
Transitioning
NOP
T13
Valid
T10
R
TT,nom
NOP
T14
ODTL off
Don’t Care
Transitioning
Valid
T15
NOP
T11
NOP
T16
Don’t Care
t AOF (MIN)
t AOF (MAX)
NOP
T17
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