MCIMX27VJP4AR2 Freescale, MCIMX27VJP4AR2 Datasheet - Page 49

• Manufacturer Part Number: MCIMX27VJP4AR2
• Manufacturer: Freescale

Specifications of MCIMX27VJP4AR2

• Lead Free Status / RoHS Status: Compliant

4.2.4
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI, SAP) and external serial interfaces (audio and voice codecs). The AC timing
of AUDMUX external pins is hence governed by SSI and SAP modules. Please refer to their respective
electrical specifications.
4.2.5
This section describes the electrical information (AC timing) of the CSI.
4.2.5.1
VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on
VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC
is high.
parameters.
Freescale Semiconductor
ATA Interface Signals
Figure 9
Digital Audio Mux (AUDMUX)
CMOS Sensor Interface (CSI)
Gated Clock Mode Timing
and
Figure 10
Figure 8. ATA interface Signals Timing Diagram
depict the gated clock mode timings of CSI, and
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
SI2
SI1
Table 21
Electrical Characteristics
lists the timing
49