MCIMX27VJP4AR2 Freescale, MCIMX27VJP4AR2 Datasheet - Page 53

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MCIMX27VJP4AR2

Manufacturer Part Number
MCIMX27VJP4AR2
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX27VJP4AR2

Lead Free Status / RoHS Status
Compliant
HCLK = AHB System Clock, THCLK = Period of HCLK
4.2.6
This section describes the electrical information of the CSPI.
4.2.6.1
Figure 13
timing parameters.
Freescale Semiconductor
and
Number
Configurable Serial Peripheral Interface (CSPI)
CSPI Timing
Figure 14
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk high time
Table 22. Non-Gated Clock Mode Parameters (continued)
show the master mode and slave mode timings of CSPI, and
Parameter
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Minimum
T
T
HCLK
HCLK
1
0
Maximum
HCLK/2
Electrical Characteristics
Table 23
MHz
Unit
ns
ns
ns
lists the
53

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