MCIMX27VJP4AR2 Freescale, MCIMX27VJP4AR2 Datasheet - Page 54

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MCIMX27VJP4AR2

Manufacturer Part Number
MCIMX27VJP4AR2
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX27VJP4AR2

Lead Free Status / RoHS Status
Compliant
CSPI1_RDY
(output)
(Input)
(Input)
Electrical Characteristics
4.3
Figure 13
lists the timing parameters. The values shown in timing diagrams were tested using a worst case core
voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V.
SCLK
(output)
MOSI
54
MISO
SCLK
MISO
MOSI
(input)
SSn
SSn
Timing Diagrams
and
t8
Figure 14
t6’
t10
t12
t6
t10
t12
depict the master mode and slave mode timing diagrams of the CSPI and
t13
t11
t13
t11
t1’
Figure 13. CSPI Master Mode Timing Diagram
t1
Figure 14. CSPI Slave Mode Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
t2’
t2
t3’
t3
t4
t4
t4
t4
t7’
t7
t5’
t9
t5
Freescale Semiconductor
Table 23

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