MCIMX27VJP4AR2 Freescale, MCIMX27VJP4AR2 Datasheet - Page 79
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MCIMX27VJP4AR2
Manufacturer Part Number
MCIMX27VJP4AR2
Description
Manufacturer
Freescale
Datasheet
1.MCIMX27VJP4AR2.pdf
(152 pages)
Specifications of MCIMX27VJP4AR2
Lead Free Status / RoHS Status
Compliant
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Freescale Semiconductor
1
Note:
SD17
SD18
SD19
SD20
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
DQM (output)
DQS (output)
DQ (output)
DQ and DQM setup time to DQS
DQ and DQM hold time to DQS
Write cycle DQS falling edge to SDCLK output delay time.
Write cycle DQS falling edge to SDCLK output hold time.
SDCLK
SDCLK
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 41. Mobile DDR SDRAM Write Cycle Timing Parameters
Figure 41. Mobile DDR SDRAM Write Cycle Timing Diagram
SD17
Table 41
SD17
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Parameter
Data
DM
indicates SDRAM requirements. All output signals
SD18
SD18
Data
DM
NOTE
Data
DM
SD17
SD17
Data
DM
SD18
SD18
Data
DM
Symbol
tDSH
tDSS
tDH
tDS
Data
DM
SD19
1
0.95
0.95
Data
DM
Min
1.8
1.8
Electrical Characteristics
SD20
Max
—
—
—
—
Data
DM
Unit
ns
ns
ns
ns
79
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