IDT82V3380PF8 IDT, Integrated Device Technology Inc, IDT82V3380PF8 Datasheet - Page 144
IDT82V3380PF8
Manufacturer Part Number
IDT82V3380PF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V3380PF8.pdf
(170 pages)
Specifications of IDT82V3380PF8
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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OUT7_FREQ_CNFG - Output Clock 7 Frequency Configuration
Programming Information
IDT82V3380
Address:71H
Type: Read / Write
Default Value: 00001000
OUT7_PATH_S
7 - 4
3 - 0
Bit
EL3
7
OUT7_PATH_SEL[3:0]
OUT7_DIVIDER[3:0]
OUT7_PATH_S
Name
EL2
6
These bits select an input to OUT7.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT7.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT7_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to
Table 25~Table 27
OUT7_PATH_S
EL1
5
Table 24
for the division factor selection.
OUT7_PATH_S
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
EL0
4
144
OUT7_DIVIDER
3
3
Description
OUT7_DIVIDER
2
2
SYNCHRONOUS ETHERNET WAN PLL
OUT7_DIVIDER
1
1
October 20, 2008
OUT7_DIVIDER
0
0
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