IDT82V3380PF8 IDT, Integrated Device Technology Inc, IDT82V3380PF8 Datasheet - Page 67
IDT82V3380PF8
Manufacturer Part Number
IDT82V3380PF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V3380PF8.pdf
(170 pages)
Specifications of IDT82V3380PF8
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Table 44: Register List and Map (Continued)
7.2
7.2.1
ID[7:0] - Device ID 1
Programming Information
IDT82V3380
Address
Address: 00H
Type: Read
Default Value: 10001000
(Hex)
7A
7B
7C
7D
71
72
73
74
78
7 - 0
Bit
ID7
OUT7_FREQ_CNFG - Output Clock 7
Frequency Configuration
OUT8_FREQ_CNFG - Output Clock 8
Frequency Configuration & Output
Clock 6, 7 & 9 Invert Configuration
OUT9_FREQ_CNFG - Output Clock 9
Frequency Configuration & Output
Clock 1 ~ 5 Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
& Multiframe Sync Output Configura-
tion
PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
PHASE_OFFSET[7:0]_CNFG - Phase
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase
Offset Configuration 2
SYNC_MONITOR_CNFG - Sync Mon-
itor Configuration
SYNC_PHASE_CNFG - Sync Phase
Configuration
7
REGISTER DESCRIPTION
GLOBAL CONTROL REGISTERS
Register Name
ID[7:0]
Name
ID6
6
Refer to the description of the ID[15:8] bits (b7~0, 01H).
ID5
OUT8_PAT
OUT9_PAT
IN_2K_4K_
_WINDOW
IN_NOISE
PH_OFFS
5
8K_INV
H_SEL
H_SEL
ET_EN
Bit 7
-
-
Synchronization Configuration Registers
PBO & Phase Offset Control Registers
OUT8_EN
OUT9_EN
OUT7_PATH_SEL[3:0]
8K_EN
Bit 6
-
-
-
ID4
SYNC_MON_LIMT[2:0]
4
T4_INPUT
T4_INPUT
PH_MON_
2K_EN
_FAIL
_FAIL
Bit 5
EN
67
-
-
AMI_OUT_
OUT5_INV OUT4_INV OUT3_INV OUT2_INV OUT1_INV
2K_8K_PU
PH_MON_
L_POSITI
ID3
PBO_EN
3
DUTY
Bit 4
PH_OFFSET[7:0]
ON
Description
-
-
400HZ_SE
8K_INV
Bit 3
L
-
-
-
ID2
2
PH_TR_MON_LIMT[3:0]
SYNCHRONOUS ETHERNET WAN PLL
OUT9_INV OUT7_INV OUT6_INV
8K_PUL
OUT7_DIVIDER[3:0]
Bit 2
-
-
-
2K_INV
ID1
1
Bit 1
PH_OFFSET[9:8]
SYNC_PH1[1:0]
-
2K_PUL
October 20, 2008
Bit 0
-
ID0
0
Reference
P 147
P 148
P 149
P 150
P 150
P 144
P 145
P 146
P 148
Page
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