TSEV83102G0BGL E2V, TSEV83102G0BGL Datasheet - Page 37

• Manufacturer Part Number: TSEV83102G0BGL
• Manufacturer: E2V

Specifications of TSEV83102G0BGL

• Lead Free Status / RoHS Status: Not Compliant

TS83102G0B Operating Features
Timing Information
Timing Value for
TS83102G0B
Propagation Time
Considerations
TOD-TDR Variation
Over Temperature
Principle of Operation
2101D–BDC–06/04
The timing values are defined in the “Electrical Operating Characteristics” on page 4.
The timing values are given at the package inputs/outputs, taking into account the package’s
transmission line, bond wire, pad and ESD protections capacitance, as well as specified termi-
nation loads. The evaluation board propagation delays in 50
are not taken into account. You should apply proper derating values corresponding to termina-
tion topology.
The TOD and TDR timing values are given from the package pin to pin and do not include the
additional propagation times between the device pins and input/output termination loads. For
the evaluation board, the propagation time delay is 6.1 ps/mm (155 ps/inch) corresponding to
a 3.4 dielectric constant (at 10 GHz) of the RO4003 used for the board.
If a different dielectric layer is used (for instance Teflon), you should use appropriate propaga-
tion time values.
TD1 and TD2 do not depend on propagation times because they are differential data (see
“Definition of Terms” on page 35).
TD1 and TD2 are also the most straightforward data to measure, because they are differential:
TD can be measured directly on the termination loads, with matching oscilloscope probes.
Values for TOD and TDR track each other over the temperature (there is a 1% variation for
TOD and TDR per 100 C temperature variation). Therefore the TOD and TDR variation over
temperature is negligible. Moreover, the internal (on-chip) skews between each TOD and TDR
data effect can be considered negligible. Consequently, the minimum values for TOD and
TDR are never more than 100 ps apart. The same is true for their maximum values.
However, the external TOD and TDR values can be dictated by the total digital data skews
between each TOD and TDR. These digital skews can include the MCM board, bonding wires
and output line length differences, as well as output termination impedance mismatches.
The external (on-board) skew effect has not been taken into account for the specification of
TOD and TDR minimum and maximum values.
The analog input is sampled on the rising edge of the external clock’s input (CLK/CLKB) after
TA (aperture delay). The digitized data is available after 4 clock periods’ latency (pipeline
delay [TPD]) on the clock’s rising edge, after a typical propagation delay TOD. The Data
Ready differential output signal frequency (DR/DRB) is half the external clock’s frequency. It
switches at the same rate as the digital outputs. The Data Ready output signal (DR/DRB)
switches on the external clock’s falling edge after a propagation delay TDR.
If TOD equals TDR, the rising edge (True-False) of the differential Data Ready signal is placed
in the middle of the Output Data Valid window. This gives maximum setup and hold times for
external data acquisition.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is
available for initializing the differential Data Ready output signal (DR/DRB). This feature is
mandatory in certain applications using interleaved ADCs or using a single ADC with demulti-
plexed outputs. Without Data Ready signal initialization, it is impossible to store the output
digital data in a defined order.
controlled impedance traces
TS83102G0B
37