TSEV83102G0BGL E2V, TSEV83102G0BGL Datasheet - Page 43

• Manufacturer Part Number: TSEV83102G0BGL
• Manufacturer: E2V

Specifications of TSEV83102G0BGL

• Lead Free Status / RoHS Status: Not Compliant

VPLUSD Digital Power
Supply Settings
ECL Differential
Output Termination
Configurations
2101D–BDC–06/04
See the recommended termination scenarios in Figures 46. and 47. below.
Note:
•
•
If used with the TS81102G0 DMUX, V
Figure 46. 50
Figure 47. Unterminated Differential Outputs (Optional)
50
For differential ECL digital output levels: V
connected to ground via a 5
For the LVDS digital output logic compatibility: V
(±75 mV).
50
VPLUSD = - 0.8V
VPLUSD = -0.8V
Since the output buffers feature a 100
drive high the input impedance storing registers without terminating the 50
Timewise, this means that the incident wave reflects at the 50
travels back to the 50
back reflection occurs and the output swing is doubled.
10.5 mA
10.5 mA
Terminated Differential Outputs (Recommended)
50
50
Zc = 50
Zc = 50
Zc = 50
data output buffer. Since the buffer output impedance is 50 , no
Zc = 50
resistor to ensure the -0.8 voltage drop).
50
PLUSD
can be set to ground.
differential output impedance, it is possible to directly
PLUSD
should be supplied with -0.8V (or
47 pF
PLUSD
50
should be tied to 1.45V
OUTB
OUT
OUTB
OUT
transmission line output and
TS83102G0B
VOL typ = -1.17V
VOH typ = -0.94V
Differential Output Swing:
±0.23V = 0.46 Vpp
Common Mode Level = -1.05V
VOL typ = -1.4V
VOH typ = -0.94V
Differential Output Swing:
±0.46V = 0.92 Vpp
Common Mode Level = -1.17V
transmission lines.
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