STM32L-DISCOVERY STMicroelectronics, STM32L-DISCOVERY Datasheet - Page 103

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STM32L-DISCOVERY

Manufacturer Part Number
STM32L-DISCOVERY
Description
BOARD, EVAL, STM32L-DISCOVERY
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets

Specifications of STM32L-DISCOVERY

Kit Contents
Board, Debugger, Programmer And Compiler
Features
128KB Flash Plus Multiple Timers, Analogue Peripherals
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32F1xx
Rohs Compliant
Yes
Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
STM32L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32L-DISCOVERY
Manufacturer:
STMicroelectronics
Quantity:
18
Part Number:
STM32L-DISCOVERY
Manufacturer:
ST
0
STM32F205xx, STM32F207xx
Table 50.
1. TBD stands for “to be defined”.
2. Based on design simulation and/or characterization results, not tested in production.
3. Depends on f
f
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
r(CK)
f(CK)
v(WS)
h(WS)
su(WS)
h(WS)
w(CKH)
w(CKL)
su(SD_MR)
su(SD_SR)
h(SD_MR)
h(SD_SR)
h(SD_MR)
h(SD_SR)
v(SD_ST)
h(SD_ST)
v(SD_MT)
h(SD_MT)
c(CK)
Symbol
(2)
(2)
(2)
(2)
(2)
(2)
(2)(3)
(2)(3)
(2)
(2)(3)
(2)
(2)(3)
(2)
(2)
(2)
(2)
I
2
PCLK
S characteristics
I
I
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Data input setup time
Data input hold time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
2
2
S clock frequency
S clock rise and fall time
. For example, if f
Parameter
Doc ID 15818 Rev 6
PCLK
(1)
=8 MHz, then T
Master
Slave
capacitive load
C
Master
Master
Slave
Slave
Master f
presc = TBD
Master receiver
Slave receiver
Master receiver
Slave receiver
Master f
Slave f
Slave transmitter
(after enable edge)
f
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
f
Master transmitter
(after enable edge)
PCLK
PCLK
L
= 50 pF
Conditions
= TBD
= TBD
PCLK
PCLK
PCLK
PCLK
= 1/f
= TBD
= TBD,
= TBD
PLCLK
=125 ns.
Electrical characteristics
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
-
-
-
-
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
-
-
-
-
-
-
-
-
-
103/163
MHz
Unit
ns

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