IDTCV141PVG8 IDT, Integrated Device Technology Inc, IDTCV141PVG8 Datasheet - Page 4

• Manufacturer Part Number: IDTCV141PVG8
• Description: IC CLK BUFFER 1-8 DIFF 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of IDTCV141PVG8

• Input: Clock
• Output: Clock
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Other names: CV141PVG8

CONTROL REGISTERS
BYTE 0
BYTE 1
BYTE 2
BYTE 3
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SRC_STOP# drive mode
PowerDown dirve mode
Output(s) Affected
Output(s) Affected
Output(s) Affected
Output(s) Affected
PLL/Bypass#
SRC_DIV2#
High_BW#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DIFF_7
DIFF_6
DIFF_5
DIFF_4
DIFF_3
DIFF_2
DIFF_1
DIFF_0
DIFF_7
DIFF_6
DIFF_5
DIFF_4
DIFF_3
DIFF_2
DIFF_1
DIFF_0
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Logically AND with HW pin
Logically AND with HW pin
Logically AND with HW pin
Description / Function
Description/Function
Description/Function
Description/Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
4
High band width
Divided by 2
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Bypass
Driven
Driven
Free
Free
Free
Free
Free
Free
Free
Free
0
0
0
0
Low band width
PLL mode
Tri-state
Tri-state
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
Normal
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
COMMERCIAL TEMPERATURE RANGE
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
Power On
Power On
Power On
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0