IDTCV141PVG8 IDT, Integrated Device Technology Inc, IDTCV141PVG8 Datasheet - Page 7

• Manufacturer Part Number: IDTCV141PVG8
• Description: IC CLK BUFFER 1-8 DIFF 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of IDTCV141PVG8

• Input: Clock
• Output: Clock
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Other names: CV141PVG8

NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. Measured at 3dB downpoint.
PWRDWN (OE_INV = 0)
The P
during two consecutive rising edges of DIF# to be recognized as a valid assertion or
de-assertion.
PWRDWN (OE_INV = 1)
DIF AC TIMING CHARACTERISTICS
PLL Bandwidth and Peaking
OUTPUT CONTROL
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
PLL bandwidth
PLL bandwidth
T
PLL Peaking
WRDWN
T
T
Duty cycle
Duty cycle
PROP
ACTIVE
T
T
T
DRIVE
Symbol
T
PROP
CCJITTER
INACTIVE
P
P
T
Symbol
ACTIVE
SKEW
WRDWN
WRDWN
,
BYPASS
_P
_P
signal is a de-bounced signal in that its state must remain unchanged
1
0
1
0
,
PLL
WR
_OE
WR
_OE
D
D
WN
WN
Parameter
SRC_IN to DIF Propagation Delay, PLL Mode
SRC_IN to DIF Propagation Delay, Bypass Mode
DIF_[7:0] Pin to Pin Skew
HIGH_BW#=0 (high bandwidth)
HIGH_BW#=1 (low bandwidth)
PLL Peaking
Cycle to Cycle Jitter
PLL Mode
Bypass (assume input is 50%)
Iref*2 or Float
Iref*2 or Float
Parameter
CLK driven from PD De_Assertion
CLK Toggling from PD De_Assertion
CLK toggling from OE_[7:0] Assertion
CLK Tri-stated from OE_[7:0] De_Assertion
Normal
Normal
(1)
DIF
DIF
(1,2)
(1)
(1)
(1)
(1)
(1)
Normal
Normal
DIF#
Float
DIF#
Float
(1)
(1)
7
SRC_STOP (OE_INV = 0)
The SRC_STOP signal is a de-bounced signal in that its state must remain unchanged
during two consecutive rising edges of DIF# to be recognized as a valid assertion or de-
assertion.
SRC_STOP (OE_INV = 1)
SRC_STOP
SRC_STOP
1
0
1
0
Min
—
—
2
2
COMMERCIAL TEMPERATURE RANGE
Iref*6 or Float
Iref*6 or Float
-250
Min
2.5
0.7
—
—
—
45
40
Normal
Normal
2
DIF
DIF
Typ
—
—
—
—
Typ
—
—
—
—
—
—
3
1
1
Max
300
1
6
6
Max
250
250
4.5
1.4
50
55
60
4
3
Normal
Normal
Clock Periods
Clock Periods
DIF#
Float
DIF#
Float
Units
μs
ms
Units
MHz
MHz
dB
pS
ps
ns
ps
%
%