ICS9FGP202AKLFT IDT, Integrated Device Technology Inc, ICS9FGP202AKLFT Datasheet - Page 2

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ICS9FGP202AKLFT

Manufacturer Part Number
ICS9FGP202AKLFT
Description
IC FREQ TIMING GENERATOR 40VFQFN
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS9FGP202AKLFT

Input
Clock
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN, 40-VFQFPN
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9FGP202AKLFT

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Pin Description
1339C—09/14/09
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
IREF
VDD32K
32.768KHz
GND32K
VDDREF
25MHz_0
25MHZ_1
GNDREF
X1_25
X2_25
GND33
33.33MHZ/**SMBADR
VDD33
RMII7
RMII6
VDDRMII
GNDRMII
RMII5
RMII4
OE_RMIIB
OE_RMIIA
RMII3
RMII2
VDDRMII
GNDRMII
RMII1
RMII0
SMBCLK
SMBDAT
VttPwr_GD/PD#
Integrated
Circuit
Systems, Inc.
PIN NAME
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PIN
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
Crystal input, Nominally 25.00MHz.
33.33MHz clock output / SMBus address select bit.
Ground pin.
Power pin for the DOT96 clocks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 = tri-state output(s)
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 = tri-state output(s)
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current.
475 ohms is the standard value.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs.
Crystal output, Nominally 25.00MHz.
Ground pin for the 33.33MHz outputs
Power pin for the 33.33MHz outputs, nominal 3.3V
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Active high input for enabling RMII(7:4) outputs.
1 = enable output(s), 0 = low
Active high input for enabling RMII(3:0) outputs.
1 = enable output(s), 0 = low
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid
and are ready to be sampled. This is an active high input. / Asynchronous active low input pin
used to power down the device into a low power state.
2
DESCRIPTION
ICS9FGP202A

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