IDTCSPU877DBVG8 IDT, Integrated Device Technology Inc, IDTCSPU877DBVG8 Datasheet

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IDTCSPU877DBVG8

Manufacturer Part Number
IDTCSPU877DBVG8
Description
IC PLL CLK DVR SDRAM 52-CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Driverr
Datasheet

Specifications of IDTCSPU877DBVG8

Input
Clock
Output
Differential
Frequency - Max
340MHz
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
52-CABGA
Frequency-max
340MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CSPU877DBVG8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDTCSPU877DBVG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate)
• Operating frequency: 125MHz to 340MHz
• Very low skew: ≤ ≤ ≤ ≤ ≤ 40ps
• Very low jitter: ≤ ≤ ≤ ≤ ≤ 40ps
• 1.8V AV
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin MLF packages
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
APPLICATIONS:
• Meets or exceeds JEDEC standard 82.8 for registered DDR2
• Along with SSTU32864/65/66, DDR2 register, provides complete
FUNCTIONAL BLOCK DIAGRAM
IDTCSPU877D
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
c
SDRAM applications
clock driver
solution for DDR2 DIMMs
2004 Integrated Device Technology, Inc.
DD
and 1.8V V
DDQ
10KΩ - 100KΩ
FBIN
FBIN
CLK
CLK
OE
OS
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
AV
DD
POWER
LOGIC
DOWN
MODE
TEST
PLL
AND
LD
1
DESCRIPTION:
to distribute one differential clock input pair(CLK, CLK ) to 10 differential
output pairs (Y
(FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization
of the outputs to the input reference is provided. OE, OS, and A
power-down and test mode logic. When A
off and bypassed for test mode purposes. When the differential clock inputs
(CLK, CLK) are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a current consumption device of less than
500µA.
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPU877D,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
+70°C). See Ordering Information for details.
LD, OS, or OE
LD or OE
PLL BYPASS
The CSPU877D is a PLL based clock driver that acts as a zero delay buffer
The CSPU877D requires no external components and has been optimised
The CSPU877D is available in Commercial Temperature Range (0°C to
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output
COMMERCIAL TEMPERATURE RANGE
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
VDD
is grounded, the PLL is turned
IDTCSPU877D
AUGUST 2004
VDD
DSC 6575/4
control the

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IDTCSPU877DBVG8 Summary of contents

Page 1

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER FEATURES: • differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤ ≤ ...

Page 2

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION GND GND GND GND BALL ...

Page 3

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION 1 V DDQ CLK CLK 5 GND V 6 DDQ AGND DDQ 10 GND MLF TOP VIEW ...

Page 4

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN DESCRIPTION (VFBGA) Pin Name AGND AV DD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND B2 - B5, C2, C5, H2, H5 D4, E2, E5, F2, ...

Page 5

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER FUNCTION TABLE (1,2) INPUTS GND H X GND H X GND L H GND L L 1.8V (nom 1.8V (nom 1.8V (nom ...

Page 6

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TIMING REQUIREMENTS Symbol Parameter (1,2,3) f Operating Clock Frequency CLK (1,3,4) Application Clock Frequency t Input Clock Duty Cycle DC (5) t Stabilization Time L NOTES: 1. The PLL will track a ...

Page 7

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS V DDQ CSPU877D GND V /2 DDQ Z = 60Ω 2.97" 60Ω 2.97" CSPU877D V /2 DDQ Z = 60Ω L ...

Page 8

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT t t cycle n cycle n jit(cc) cycle n ...

Page 9

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT ...

Page 10

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS OE Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y) CLK CLK FBIN FBIN SSC OFF SSC ON t (Ø)DYN 50% ...

Page 11

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 80% Clock Inputs and Outputs SLR(I/O) BEAD VIA 1Ω 0603 CARD V DDQ 4.7uF 1206 GND VIA CARD NOTES: Place all ...

Page 12

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER APPLICATION INFORMATION CLK R = 120Ω 10pF CLK R = 120Ω 10pF Feedback path CLK R = 120Ω 10pF CLK R = 120Ω 10pF ...

Page 13

IDTCSPU877D 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER ORDERING INFORMATION XXXXX XX IDTCSPU Package Device Type CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 X Process Blank 0°C to +70°C (Commercial) BV Very Fine Pitch Ball Grid Array BVG ...

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