ICS950218AFLFT IDT, Integrated Device Technology Inc, ICS950218AFLFT Datasheet

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ICS950218AFLFT

Manufacturer Part Number
ICS950218AFLFT
Description
IC TIMING CTRL HUB P4 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet
1.ICS950218AFLFT.pdf (19 pages)

Specifications of ICS950218AFLFT

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
950218AFLFT
Recommended Application:
Brookdale and Brookdale-G chipset with P4 processor.
Output Features:
•
•
•
•
•
•
•
Frequency Table
0466B—03/17/04
i B
F
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2 t
4
3 - Pairs of differential CPU clocks (differential current
mode)
3 - 3V66 @ 3.3V
10 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
2 - REF @ 3.3V, 14.318MHz
1 - 48_66MHz selectable @ 3.3V fixed
1 - 24_48MHz selectable @ 3.3V
i B
F
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7 t
3
Integrated
Circuit
Systems, Inc.
F
i B
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6 t
2
i B
F
S
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
5 t
1
Programmable Timing Control Hub™ for P4™
F
i B
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4 t
0
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
P
6
6
M
0
0
0
1
1
1
2
2
2
3
3
4
4
4
5
5
6
6
6
7
7
8
8
9
0
3
0
0
0
3
6
6
U
2
5
8
1
4
7
0
3
6
0
6
0
4
8
2
6
0
4
6
0
5
0
5
0
0
3
0
0
0
3
H
8 .
6 .
C
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
6 .
0 .
0 .
0 .
0 .
0 .
2 .
6 .
4 .
0 .
0 .
3 .
z
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
K
6
7
7
7
7
7
8
8
7
7
6
7
7
7
7
7
8
8
6
6
7
7
7
7
6
6
6
6
6
6
6
6
3
M
V
8
0
2
4
6
8
0
2
2
4
8
0
2
4
6
8
0
2
6
8
0
2
4
6
6
6
6
6
6
6
6
6
H
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
3 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
6 .
0 .
0 .
0 .
0 .
0 .
8 .
8 .
8 .
8 .
6 .
6 .
6 .
6 .
6
z
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
3
3
3
3
3
3
4
4
3
3
3
3
3
3
3
3
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
C
M
4
5
6
7
8
9
0
1
6
7
4
5
6
7
8
9
0
1
3
4
5
6
7
8
3
3
3
3
3
3
3
3
C I
H
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
1 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
3 .
0 .
0 .
0 .
0 .
0 .
4 .
4 .
4 .
4 .
3 .
3 .
3 .
3 .
L
z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
K
Pin Configuration
**
SEL48_24#/PCICLK2
*MULTISEL1/REF1
*FS1/24_48MHz
Features/Benefits:
•
•
•
•
•
•
•
•
•
Key Specifications:
•
•
•
*FS2/PCICLK0
*FS3/PCICLK1
*FS4/PCICLK3
Vtt_PWRGD#
1
*FS0/48MHz
1 This output has 2X drive
* Internal Pull-up resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
operations.
Uses external 14.318MHz crystal.
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
VDDREF
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9
RESET#
VDDPCI
VDDPCI
AVDD48
GND
GND
GND
X1
X2
48-Pin 300-mil SSOP
2
C Index read/write and block read/write
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/MULTSEL0*
GND
VDDCPU
CPUCLKT2
CPUCLKC2
GND
PD#
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
I REF
AVDD
GND
VDD3V66
3V66_0
3V66_1
GND
3V66_2
3V66_48MHz/SEL66_48#
SCLK
SDATA
ICS950218
*

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ICS950218AFLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ Recommended Application: Brookdale and Brookdale-G chipset with P4 processor. Output Features: • Pairs of differential CPU clocks (differential current mode) • 3V66 @ 3.3V • 10 ...

Page 2

Integrated Circuit Systems, Inc. General Description The ICS950218 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950218 is ...

Page 3

Integrated Circuit Systems, Inc. Pin Description ...

Page 4

Integrated Circuit Systems, Inc. Maximum Allowed Current ...

Page 5

Integrated Circuit Systems, Inc. General I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...

Page 6

Integrated Circuit Systems, Inc. Byte 0: Functionality and frequency select register (Default= ...

Page 7

Integrated Circuit Systems, Inc. Byte 1: Output Control Register (1 = enable disable ...

Page 8

Integrated Circuit Systems, Inc. Byte 5: Programming Edge Rate (1 = enable disable ...

Page 9

Integrated Circuit Systems, Inc. Byte 8: Byte Count Read Back Register ...

Page 10

Integrated Circuit Systems, Inc. Byte 12: VCO Frequency N Divider (VCO divider) Control Register ...

Page 11

Integrated Circuit Systems, Inc. Byte 16: Output Divider Control Register ...

Page 12

Integrated Circuit Systems, Inc. Byte 19: Group Skew Control Register ...

Page 13

Integrated Circuit Systems, Inc. Byte 23: Slew Rate Control Register ...

Page 14

Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow ...

Page 15

Integrated Circuit Systems, Inc. Electrical Characteristics - 3V66 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Output Frequency Output Impedance R DSP1 1 Output High Voltage Output Low Voltage V OL ...

Page 16

Integrated Circuit Systems, Inc. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Output Frequency F O1 Output Impedance R DSP1 1 Output High Voltage Output Low ...

Page 17

Integrated Circuit Systems, Inc. Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 18

Integrated Circuit Systems, Inc. Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between ...

Page 19

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package ...

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