ICS93V857BG-025LFT IDT, Integrated Device Technology Inc, ICS93V857BG-025LFT Datasheet - Page 2

IC CLOCK DRIVER 2.5V 48-TSSOP

ICS93V857BG-025LFT

Manufacturer Part Number
ICS93V857BG-025LFT
Description
IC CLOCK DRIVER 2.5V 48-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS93V857BG-025LFT

Input
Clock
Output
Clock
Frequency - Max
233MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
233MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
93V857BG-025LFT
Pin Descriptions
This PLL Clock Buffer is designed for a V
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AV
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0°C to 85°C.
0693M—02/19/09
ICS93V857-XXX
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