IDTCSPUA877BVG IDT, Integrated Device Technology Inc, IDTCSPUA877BVG Datasheet

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IDTCSPUA877BVG

Manufacturer Part Number
IDTCSPUA877BVG
Description
IC PLL CLK DVR SDRAM 52-CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Driverr
Datasheet

Specifications of IDTCSPUA877BVG

Input
Clock
Output
Differential
Frequency - Max
410MHz
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
52-CABGA
Frequency-max
410MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CSPUA877BVG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDTCSPUA877BVG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDTCSPUA877BVG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate)
• Operating frequency: 125MHz to 410MHz
• Stabilization time: <6us
• Very low skew: ≤ ≤ ≤ ≤ ≤ 40ps
• Very low jitter: ≤ ≤ ≤ ≤ ≤ 40ps
• 1.8V AV
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in VFBGA package
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
COMMERCIAL TEMPERATURE RANGE
APPLICATIONS:
• Meets or exceeds JEDEC standard CUA877 for registered DDR2
• Along with SSTUA32864/66, DDR2 register, provides complete
FUNCTIONAL BLOCK DIAGRAM
IDTCSPUA877
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
c
SDRAM applications
clock driver
solution for DDR2 DIMMs
2006 Integrated Device Technology, Inc.
DD
and 1.8V V
DDQ
10KΩ - 100KΩ
FBIN
FBIN
CLK
CLK
OS
OE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
AV
DD
POWER
LOGIC
DOWN
MODE
TEST
PLL
1
AND
LD
DESCRIPTION:
to distribute one differential clock input pair(CLK, CLK ) to 10 differential
output pairs (Y
(FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization
of the outputs to the input reference is provided. OE, OS, and A
power-down and test mode logic. When A
off and bypassed for test mode purposes. When the differential clock inputs
(CLK, CLK) are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a clock driver current consumption of less
than 500μA.
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPUA877 ,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
+70°C). See Ordering Information for details.
The CSPUA877 is a PLL based clock driver that acts as a zero delay buffer
The CSPUA877 requires no external components and has been optimised
The CSPUA877 is available in Commercial Temperature Range (0°C to
LD, OS, or OE
LD or OE
PLL BYPASS
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output
COMMERCIAL TEMPERATURE RANGE
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
VDD
is grounded, the PLL is turned
IDTCSPUA877
OCTOBER 2006
VDD
DSC-6518/9
control the

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IDTCSPUA877BVG Summary of contents

Page 1

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER FEATURES: • differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 410MHz • Stabilization time: <6us • Very ...

Page 2

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION GND GND GND GND BALL VFBGA PACKAGE ...

Page 3

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER ABSOLUTE MAXIMUM RATINGS Symbol Rating Supply Voltage Range DDQ DD I (3) V Input Voltage Range O (3) V Voltage range applied to any output in the high or ...

Page 4

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN DESCRIPTION (VFBGA) Pin Name AGND AV DD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND B2 - B5, C2, C5, H2, H5 D4, E2, E5, F2, ...

Page 5

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C A Symbol Parameter V Input Clamp Voltage (All Inputs (2) V Input ...

Page 6

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER AC ELECTRICAL CHARACTERISTICS Symbol Description any Y any Y/Y DIS s Output Enable (OE) LR(I) Input Clock Slew Rate, measured single-ended LR(O) (4) s Output ...

Page 7

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS V DDQ CSPUA877 GND V /2 DDQ Z = 60Ω 2.97" 60Ω 2.97" CSPUA877 V /2 DDQ Z = 60Ω L ...

Page 8

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT t t cycle n cycle n jit(cc) cycle n ...

Page 9

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT NOTE Average input frequency measured at CLK / CLK Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT ...

Page 10

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS OE Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y) CLK CLK FBIN FBIN SSC OFF SSC ON t (Ø)DYN 50% ...

Page 11

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 80% Clock Inputs and Outputs, OE 20% t SLR(I/O) BEAD VIA 1Ω 0603 CARD V DDQ GND VIA CARD NOTES: Place all decoupling capacitors as close to ...

Page 12

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER APPLICATION INFORMATION CLK R = 120Ω CLK R = 120Ω 10pF Feedback path CLK R = 120Ω CLK R = 120Ω 10pF Feedback path ~2.5" CSPUA877 Z = ...

Page 13

IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER ORDERING INFORMATION IDTCSPUA XXXXX XX Package Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process Blank 0°C to +70°C (Commercial) BVG Very Fine Pitch Ball Grid ...

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