ICS93776AFT IDT, Integrated Device Technology Inc, ICS93776AFT Datasheet - Page 2

• Manufacturer Part Number: ICS93776AFT
• Description: IC DDR PLL ZD BUFFER 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of ICS93776AFT

• Input: Clock
• Output: Clock
• Frequency - Max: 340MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 340MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 93776AFT

ICS93776
Pin Descriptions
0793A—03/08/05
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
DDRT2
DDRC2
GND
DDRC3
DDRT3
FB_OUTC
FB_OUTT
FB_INT
FB_INC
SDATA
VDD
DDRT4
DDRC4
DDRT5
DDRC5
GND
PIN TYPE DESCRIPTION
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
IN
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
IN
IN
I/O
PWR
OUT
OUT
OUT
OUT
PWR
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
"True" reference clock input.
"Complementary" reference clock input.
2.5V power for the PLL core.
Ground pin.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Complement single-ended feedback output, dedicated
external feedback. It switches at the same frequency
as other DDR outputs, This output must be connect to
FB_INC.
True single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other
DDR outputs, This output must be connect to FB_INT.
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with
CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides
feedback signal to internal PLL for synchronization
with CLK_INT to eliminate phase error.
Data pin for SMBus circuitry, 5V tolerant.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
2