ICS9FG1904BK-1LF IDT, Integrated Device Technology Inc, ICS9FG1904BK-1LF Datasheet - Page 12

• Manufacturer Part Number: ICS9FG1904BK-1LF
• Description: IC FREQUENCY GENERATOR 72-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG1904BK-1LF

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, 72-VFQFPN
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9FG1904BK-1LF

Using M/N Programming to Obtain Other Gear Ratios
M/N programming can be used to obtain input output frequency combinations that are not preconfigured in the
9FG1904B-1. Refer to Figure 2 PLL Block Diagram.
The internal architecture of the 9FG1904B-1 is standard pseudo-ZDB architecture with internal feedback. This means
that the REF divider, the Output divider and the Feedback divider all play a role in determining the output frequency.
The output frequency is given by the equation:
The DBxxxxGSO input/output combinations that are not in the 9FG1904B-1 gear table are shown in Table 1 DBxxxxGSO
Gears Not Present in the 9FG1904B-1 . This table also gives the values needed to program the gearing PLL to provide
the desired input/output combination.
Note before the M/N programming can be accomplished, Byte 10, bit 7 (the M/N_Enable bit) must be set to a ‘1’. The
values provided in the table above have been verified to meet the specified performance of the 9FG1901B-1.
Performance is not guaranteed for any other values that have not been pre-approved by IDT. Contact your local IDT
representative for other values not mentioned here.
Setting the 1:1 PLL Operating Point
After configuring the Gearing outputs, it is also necessary to set the 1:1 PLL operating point by writing the input
frequency value to Byte 9 bits (2:0). The input frequency is usually the CPU HCLK frequency.
1255B—08/03/07
Clock
Input
Figure 2 PLL Block Diagram
Integrated
Circuit
Systems, Inc.
Table 1 DBxxxxGSO Gears Not Present in the 9FG1904B-1
Line
1
2
3
REF (M)
FBK (N)
DIV
DIV
0
1
1
133.33
400.00
400.00
Output Frequency = (Input Frequency x N x Output Div)/M
400.00
200.00
266.67
vco
12
12
4
12
Gear PLL Bytes
6
8
1:1 PLL Bytes
12
2
4
3
OUTPUT
DIV
3.000
0.500
0.667
Byte
Byte
17
11
A
A
2
BUFFERS
Byte
Byte
18
12
A
4
6
ICS9FG1904B-1
Byte
Byte
19
13
0
4
1
Output
Clocks