ICS950810CFLF IDT, Integrated Device Technology Inc, ICS950810CFLF Datasheet - Page 16

• Manufacturer Part Number: ICS950810CFLF
• Description: IC FREQ GEN 200MHZ CLK 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS950810CFLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950810CFLF

PD# - Assertion (transition from logic "1" to logic "0")
ICS950810
0472F—01/12/04
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
REF 14.318MHz
CPUT 100MHz
CPUC 100MHz
USB 48MHz
PCI 33MHz
3V66MHz
PD #
0ns
Power Down Assertion of Waveforms
25ns
16
50ns
2
C Bit 6 of Byte 0 is programmed