ICS950810CFLF IDT, Integrated Device Technology Inc, ICS950810CFLF Datasheet
ICS950810CFLF
Specifications of ICS950810CFLF
Related parts for ICS950810CFLF
ICS950810CFLF Summary of contents
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Integrated Circuit Systems, Inc. Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets. Output Features: • 3 0.7V Differential CPU Clock Pairs • 7 PCI (3.3V) @ 33.3MHz • 3 PCI_F ...
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ICS950810 Pin Configuration ...
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Pin Configuration (Continued ...
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ICS950810 Power Groups (Analog) (Digital) VDDA = PLL1 VDDPCI VDD48 = 48MHz, PLL VDD3V66 VDDREF = VDD for Xtal, POR VDDCPU Truth Table ...
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Power Management PD# CPU_STOP# PCI_STOP Note: PCI_F is not affected by PCI_STOP# and CPU_STOP# Tri-State Control of CPU Outputs Byte0 bit6 Byte1bit6 State PD# Cpu_stop# ...
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ICS950810 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . ...
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Electrical Characteristics - CPU (0.7V Select 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Current Source Output Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) ...
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ICS950810 Electrical Characteristics - 3V66 Mode: 3V66 [5: 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Output Impedance R Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle ...
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Electrical Characteristics - REF 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Output Impedance R Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter t 1 Guaranteed ...
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ICS950810 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS ...
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I2C Tables Affected Pin BYTE 0 Pin # Name Bit 7 - Spread Enabled Bit 6 - CPU_T(2:0) Bit 5 35 3V66_1/VCH_CLK Bit 4 53 CPU_STOP#* Bit 3 34 PCI_STOP#* Bit 2 40 FS2 Bit 1 55 FS1 Bit 0 ...
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ICS950810 BYTE Affected Pin 2 Pin # Name Bit Bit 6 18 PCICLK6 Bit 5 17 PCICLK5 Bit 4 16 PCICLK4 Bit 3 13 PCICLK3 Bit 2 12 PCICLK2 Bit 1 11 PCICLK1 Bit 0 10 PCICLK0 ...
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BYTE Affected Pin 5 Pin # Name Bit Bit Bit Bit Bit Bit Bit Bit BYTE ...
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ICS950810 All 3V66 clocks are pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag ...
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CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I assertion of CPU_STOP# are to be stopped after their next transition. When the ...
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ICS950810 PD# - Assertion (transition from logic "1" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to ...
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PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup ...
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ICS950810 INDEX INDEX AREA AREA 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS950810yFLF-T Example: ICS XXXX y F ...
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INDEX INDEX AREA AREA aaa 6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil) Ordering Information ICS950810yGLF-T Example: ICS XXXX y G LF- T Designation ...