ICS954204CGLF IDT, Integrated Device Technology Inc, ICS954204CGLF Datasheet - Page 14

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ICS954204CGLF

Manufacturer Part Number
ICS954204CGLF
Description
IC TIMING CTRL HUB P4 56-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS954204CGLF

Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
954204CGLF
CLKREQ# - Assertion (transition from logic “1” to logic “0”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in
Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active.
CLKREQ# - De-Assertion (transition from logic “0” to logic “1”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate
condition per the timing found in Table 4. The clock will become inactive in a glitch free manner.
0933D—03/16/05
1
Table 3. Power-Up CLKREQ# Timing
Table 4. CLKREQ# Control Timing
This timing is valid only after system clocks are stable.
T
Symbol
Symbol
T
T
T
SRCSTBL
PVCRL
CRHoff
CRHon
Integrated
Circuit
Systems, Inc.
CLKREQ#
V
SRCCLK
PCIEXDEV
SRC Clock Stablilzation Time from assertion
CLKREQ#
CLKREQ# De-asserted High to SRCCLK
Power Valid to CLKREQ# Output Active
CLKREQ# Asserted LOW to SRCCLK
SRCCLK
of CLKREQ# (Fig. 1)
Parked (Fig. 2)
Active (Fig. 2)
Parameter
Parameter
(Fig. 1)
Figure 1. Power-Up CLKREQ# Timing
Figure 2. CLKREQ# Control Timing
1
T
PVCRL
14
Power Stable to Device
T
SRCSTBL
Min
Min
0
Max
Max
100
800
0.4
Units
Units
ICS954204
µs
µs
µs
µs

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