ICS954204CGLF IDT, Integrated Device Technology Inc, ICS954204CGLF Datasheet - Page 6

• Manufacturer Part Number: ICS954204CGLF
• Description: IC TIMING CTRL HUB P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS954204CGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 954204CGLF

Absolute Max
0933D—03/16/05
1
2
3
Symbol
Electrical Characteristics - Input/Supply/Common Output Parameters
T
Tambient
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
ESD prot
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
A
VDD_In
Low Threshold Input High
VDD_A
Operating Supply Current
Low Threshold Input Low
Low-level Output Voltage
Tcase
= 0 - 70°C; Supply Voltage V
Modulation Frequency
Clock/Data Fall Time
Powerdown Current
Ts
Tdrive_CPU_STOP
Trise_CPU_STOP#
Input Capacitance
Input High Voltage
Input High Current
Clk Stabilization
Input Low Voltage
Input Low Current
Tfall_CPU_STOP
Input Frequency
Pin Inductance
Current sinking
SMBus Voltage
PARAMETER
SCLK/SDATA
SCLK/SDATA
Tdrive_SRC
Tdrive_PD
Trise_PD
Tfall_PD
Voltage
Voltage
Integrated
Circuit
Systems, Inc.
Parameter
3.3V Logic Input Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
1,2
1
human body model
Case Temperature
3
1
DD
SYMBOL
I
I
I
V
DD3.3OP
DD3.3PD
= 3.3 V +/-5%
T
PULLUP
C
T
T
C
V
L
V
V
C
V
I
I
IH_FS
STAB
I
RI2C
FI2C
IL1
IL2
F
OUT
IH
pin
INX
DD
OL
IH
IN
IL
i
V
Differential output enable after
IN
assertion of PD# to 1st clock
V
all differential pairs tri-stated
From V
Full Active, C
IN
CPU_STOP de-assertion
SDATA, SCLK @ I
= 0 V; Inputs with no pull-up
SRC output enable after
PCI_STOP de-assertion
CPU output enable after
CPU_STOP rise time of
Output pin capacitance
CPU_STOP fall time of
Triangular Modulation
= 0 V; Inputs with pull-up
(Min VIH + 0.15) to
(Max VIL - 0.15) to
all diff pairs driven
PD# de-assertion
Min
(Max VIL - 0.15)
PD# rise time of
PD# fall time of
CONDITIONS
GND - 0.5
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
DD
V
V
V
resistors
resistors
DD
OL
2000
IN
Power-Up or de-
-65
0
= 3.3 V
= 0.4 V
= V
L
= Full load;
DD
PULLUP
Max
6
V
V
DD
DD
150
115
+ 0.5V
+ 0.5V
70
V
V
SS
SS
-200
MIN
0.7
2.7
30
-5
-5
2
4
- 0.3
- 0.3
Units
°C
°C
°
V
V
V
C
14.31818
TYP
275
1.3
64
5
V
V
DD
DD
MAX
1000
0.35
400
300
300
0.8
1.8
5.5
0.4
70
12
33
10
10
5
7
5
6
5
5
5
5
5
+ 0.3
+ 0.3
UNITS
MHz
kHz
ICS954204
mA
mA
mA
mA
nH
ms
uA
uA
uA
pF
pF
pF
ns
us
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
V
NOTES
1,2
1,3
1,3
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
1
1
2
1
1
1