MPC96877VK IDT, Integrated Device Technology Inc, MPC96877VK Datasheet - Page 6

• Manufacturer Part Number: MPC96877VK
• Description: IC CLK DRIVER 1:10 SDRAM 52-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MPC96877VK

• Input: Clock
• Output: SSTL-18
• Frequency - Max: 340MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-BGA
• Frequency-max: 340MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
MPC96877
Table 5. Electrical Characteristics Over Recommended Free-Air Operating Temperature Range
1. Total I
Table 6. Timing Requirements Over Recommended Free-Air Operating Temperature Range
1. The PLL must be able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing
3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power
552
All inputs
High output voltage
Low output voltage
Output disable current
Output differential voltage
Input leakage current
Static supply current I
Dynamic Supply current
I
calculation
Operating clock frequency
Application clock frequency
Input clock duty cycle
Stabilization time
DDQ
supply and C
parameters. (Used for low speed system debug.)
up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal
to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may
be left floating after they have been driven low for one complete clock cycle.
+ I
ADD,
DD
Description
= I
see Note 1 for CPD
DDQ
PD
4
is the Power Dissipation Capacitance.
+ I
DDQ
ADD
1, 2
+ I
= F
1, 3
ADD
CK
* C
Timing Requirements
PD
Parameter
* V
I
V
I
V
DDLD
V
I
DDQ
V
ODL
DD
OH
OD
I
OL
IK
I
, solving for C
OE, OS, FBIN, FBIN
Affected Pins
CK, CK
PD
= (I
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
DDQ
+ I
6
ADD
OE = L, V
CK and CK = 270 MHz
)/(F
V
Test Conditions
V
all outputs open
I
I
CK and CK = L
CK
I
= V
OH
= V
I
I
OL
OH
I
I
OL
I
* V
= –18mA
= –100 µA
DDQ
DDQ
= 100 µA
= –9 mA
ODL
= 9 mA
DDQ
or GND
or GND
= 100 mV
) where F
AV
Min
125
160
DD
40
CK
, V
AV
is the input Frequency, V
1.7 to 1.9 V
1.7 to 1.9 V
DDQ
DD
1.7 V
1.7 V
1.7 V
1.7 V
1.7 V
1.9 V
1.9 V
1.9 V
1.9 V
, V
= 1.8 V ± 0.1 V
DDQ
Max
V
340
340
60
15
DDQ
Min
100
1.1
0.5
–0.2
DDQ
is the power
Max
± 250
–1.2
± 10
500
300
0.1
0.6
Unit
MHz
MHz
NETCOM
µs
%
MPC96877
Unit
mA
µA
µA
µA
V
V
V
V