ICS83021AMILF IDT, Integrated Device Technology Inc, ICS83021AMILF Datasheet - Page 7

• Manufacturer Part Number: ICS83021AMILF
• Description: IC FANOUT BUFFER SGL I/O 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Buffer/Driver, Translatorr

Specifications of ICS83021AMILF

• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/No
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 350MHz
• Logical Function: Translator
• Operating Supply Voltage (typ): 2.5/3.3V
• Package Type: SOIC
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.375V
• Abs. Propagation Delay Time: 2.5ns
• Mounting: Surface Mount
• Pin Count: 8
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1100; 800-1100-5; 800-1100; 83021AMILF

Parameter Measurement Information, continued
Propagation Delay
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
ICS83021I
1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
nCLK
CLK
Q0
V
DD
2
t
PD
DD
= 3.3V, V_REF should be 1.25V and
DD
/2 is
7
Output Duty Cycle/Pulse Width/Period
Figure 1. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
Q0
C1
0.1u
t
V_REF
PW
odc =
ICS83031AMI REV. C OCTOBER 31, 2008
t
t
PERIOD
PERIOD
t
PW
V
R1
1K
R2
1K
DD
2
V
x 100%
DD
CLK
nCLK