IDT5T9302PGGI8 IDT, Integrated Device Technology Inc, IDT5T9302PGGI8 Datasheet - Page 10

• Manufacturer Part Number: IDT5T9302PGGI8
• Description: IC CLK BUFFER 1:2 LVDS 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TERABUFFER™ IIr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of IDT5T9302PGGI8

• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Input: CML, eHSTL, HSTL, LVDS, LVEPECL, LVPECL, LVTTL
• Output: LVDS
• Frequency - Max: 450MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 450MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 450MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5T9302PGGI8

Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
NOTE 1: Pulse skew is calculated using the following expression:
tsk(p) =
Note that the tp
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Enable Showing Runt Pulse Generation
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time
the G signal to avoid this problem.
IIDT™ LVDS CLOCK BUFFER TERABUFFER™ II
A
IDT5T9302
2.5V LVDS 1:2 CLOCK BUFFER TERABUFFER™ II
[1:2]
A
Qn - Qn
[1:2]
Qm - Qm
- A
Qn - Qn
|
tp
[1:2]
GL
- A
HL
G
– tp
[1:2]
HL
LH
and tp
|
LH
shown above are not valid measurements for this calculation because they are not taken from the same pulse.
t
PLH
t
PLH
t
1/fo
SK(O)
t
PGD
10
t
SK(O)
t
PHL
t
PGE
IDT5T9302 REV. A APRIL 29, 2008
+ V
V
- V
+ V
V
- V
+ V
V
- V
PRELIMINARY
DIF
DIF
DIF
+ V
V
- V
V
V
V
V
V
V
+ V
V
- V
DIF
DIF
DIF
DIF
DIF
DIF
DIF
IH
THI
IL
IH
THI
IL
DIF
DIF
DIF
= 0
= 0
= 0
DIF
DIF
= 0
= 0