ICS85211AMI-01LFT IDT, Integrated Device Technology Inc, ICS85211AMI-01LFT Datasheet - Page 8

• Manufacturer Part Number: ICS85211AMI-01LFT
• Description: IC FANOUT BUFFER 1-2 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS85211AMI-01LFT

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: HSTL
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85211AMI-01LFT

This section provides information on power dissipation and junction temperature for the ICS85211I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
85211AMI-01
ABLE
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
6. T
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW
Total Power
The equation for Tj is as follows: Tj =
Tj = Junction Temperature
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
85°C + 0.241W * 103.3°C/W = 110°C. This is well below the limit of 125°C.
JA
A
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
HERMAL
R
MAX
ESISTANCE
_MAX
MAX
= V
(3.465V, with all outputs switching) = 76.2mW + 164.7mW = 240.9mW
= 82.34mW/Loaded Output pair
DD_MAX
* I
JA
DD_MAX
FOR
JA
P
DD
8-
= 3.465V * 22mA = 76.2mW
by Velocity (Linear Feet per Minute)
= 3.3V + 5% = 3.465V, which gives worst case results.
PIN
OWER
JA
SOIC, F
* Pd_total + T
C
www.idt.com
ORCED
ONSIDERATIONS
A
8
C
153.3°C/W
112.7°C/W
ONVECTION
D
0
IFFERENTIAL
128.5°C/W
103.3°C/W
200
-
TO
-HSTL F
JA
ICS85211I-01
must be used. Assuming a
L
115.5°C/W
OW
97.1°C/W
500
ANOUT
S
KEW
REV. B AUGUST 4, 2010
, 1-
B
UFFER
TO
-2