ICS853031AYLF IDT, Integrated Device Technology Inc, ICS853031AYLF Datasheet - Page 13
![IC FANOUT BUFF LVPECL/ECL 32LQFP](/photos/6/52/65269/ics853031aylf_sml.jpg)
ICS853031AYLF
Manufacturer Part Number
ICS853031AYLF
Description
IC FANOUT BUFF LVPECL/ECL 32LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet
1.ICS853031AYLF.pdf
(21 pages)
Specifications of ICS853031AYLF
Number Of Circuits
1
Ratio - Input:output
2:9
Differential - Input:output
Yes/Yes
Input
CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
ECL, LVPECL
Frequency - Max
1.6GHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
1.6GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1162
853031AYLF
853031AYLF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS853031AYLF
Manufacturer:
ICS
Quantity:
33
Company:
Part Number:
ICS853031AYLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
ICS853031AYLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
T
IDT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
ERMINATION FOR
ICS853031
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5, 3.3V LVPECL/ECL FANOUT BUFFER
™
RTT =
/ ICS
™
((V
F
1-TO-9, 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
FOUT
IGURE
OH
+ V
OL
6A. LVPECL O
) / (V
3.3V LVPECL O
1
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
Z
o
50
UTPUT
UTPUTS
T
RTT
ERMINATION
50
V
CC
FIN
- 2V
13
drive 50 transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 6A and 6B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
FOUT
F
IGURE
6B. LVPECL O
Z
Z
o
o
= 50
= 50
ICS853031AY REV. C AUGUST 12, 2008
125
84
UTPUT
3.3V
125
84
T
ERMINATION
FIN