LMK03000CISQ/NOPB National Semiconductor, LMK03000CISQ/NOPB Datasheet - Page 12

• Manufacturer Part Number: LMK03000CISQ/NOPB
• Description: IC CLOCK CONDITIONER PREC 48-LLP
• Manufacturer: National Semiconductor
• Type: Clock Conditionerr

Specifications of LMK03000CISQ/NOPB

• Pll: Yes
• Input: Clock
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.296GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 1.296GHz
• For Use With: LMK03000CEVAL - BOARD EVALUATION LMK03000C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK03000CISQ; LMK03000CISQTR

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1.0 Functional Description
The LMK03000 family of precision clock conditioners com-
bine the functions of jitter cleaning/reconditioning, multiplica-
tion, and distribution of a reference clock. The devices
integrate a Voltage Controlled Oscillator (VCO), a high per-
formance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, three LVDS, and five LVPECL clock out-
put distribution blocks.
The devices include internal 3rd and 4th order poles to sim-
plify loop filter design and improve spurious performance. The
1st and 2nd order poles are off-chip to provide flexibility for
the design of various loop filter bandwidths.
The LMK03000 family has multiple options for VCO frequen-
cies. The VCO output is optionally accessible on the Fout port.
Internally, the VCO output goes through an VCO Divider to
feed the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
1.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 µF capacitor connected to Vcc. This is important
for low noise performance.
1.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a
10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.
1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference
signal. Due to an internal DC bias the OSCin port should be
AC coupled, refer to the System Level Diagram in the Appli-
cation Information section. The OSCin port may be driven
single-endedly by AC grounding OSCin* with a 0.1 µF capac-
itor.
1.4 LOW NOISE, FULLY INTEGRATED VCO
The LMK03000 family of devices contain a fully integrated
VCO. In order for proper operation the VCO uses a frequency
calibration algorithm. The frequency calibration algorithm is
activated any time that the R15 register is programmed. Once
R15 is programmed the temperature may not drift more than
the maximum allowable drift for continuous lock, ΔT
the VCO is not guaranteed to stay in lock.
For the frequency calibration algorithm to work properly OS-
Cin must be driven by a valid signal when R15 is programmed.
1.5 CLKout DELAYS
Each individual clock output includes a delay adjustment.
Clock output delay registers (CLKoutX_DLY) support a 150
ps step size and range from 0 to 2250 ps of total delay.
1.6 LVDS/LVPECL OUTPUTS
By default all the clock outputs are disabled until pro-
grammed.
Each LVDS or LVPECL output may be disabled individually
by programming the CLKoutX_EN bits. All the outputs may
CL
, or else
12
be disabled simultaneously by pulling the GOE pin low or
programming EN_CLKout_Global to 0.
The duty cycle of the LVDS and LVPECL clock outputs are
shown in the table below.
1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* pin synchronizes the clock outputs. When the
SYNC* pin is held in a logic low state, the divided outputs are
also held in a logic low state. The bypassed outputs will con-
tinue to operate normally. Shortly after the SYNC* pin goes
high, the divided clock outputs are activated and will all tran-
sition to a high state simultaneously. All the outputs, divided
and bypassed, will now be synchronized. Clocks in the by-
passed state are not affected by SYNC* and are always
synchronized with the divided outputs.
The SYNC* pin must be held low for greater than one clock
cycle of the output of the VCO Divider, also known as the
distribution path. Once this low event has been registered, the
outputs will not reflect the low state for four more cycles. This
means that the outputs will be low on the fifth rising edge of
the distribution path. Similarly once the SYNC* pin becomes
high, the outputs will not simultaneously transition high until
four more distribution path clock cycles have passed, which
is the fifth rising edge of the distribution path. See the timing
diagram in
grammed as CLKout0_MUX = Bypassed, CLKout1_MUX =
Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and
CLKout2_DIV = 4. To synchronize the outputs, after the low
SYNC* event has been registered, it is not required to wait for
the outputs to go low before SYNC* is set high.
The SYNC* pin provides an internal pull-up resistor as shown
on the functional block diagram. If the SYNC* pin is not ter-
minated externally the clock outputs will operate normally. If
the SYNC* function is not used, clock output synchronization
is not guaranteed.
VCO_DIV
2, 4, 6, 8
Any
3
5
7
Figure 1
FIGURE 1. SYNC* Timing Diagram
Divided, or Divided and Delayed
Bypassed, or Delayed
Bypassed, or Delayed
Bypassed, or Delayed
for further detail. The clocks are pro-
CLKoutX_MUX
Any
Cycle
Duty
20211404
50%
50%
33%
40%
43%