FS6370-01G-XTD ON Semiconductor, FS6370-01G-XTD Datasheet
FS6370-01G-XTD
Specifications of FS6370-01G-XTD
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FS6370-01G-XTD Summary of contents
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... Accepts 5 MHz to 27 MHz crystal resonators 2.0 Description The FS6370 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three EEPROM-programmable phase-locked loops (PLLs) driving four programmable muxes and post dividers provide a high degree of flexibility. ...
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... FS6370 Table 1: Pin Descriptions Pin Type Name Description 1 P VSS Ground SEL_CD Selects one of two programmed PLL C, Mux C/D and post divider C/D combinations PD/SCL Power-down input (run-mode) or serial interface clock input (program mode VSS Ground 5 AI XIN Crystal oscillator feedback ...
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... FS6370 3.0 Functional Block Description 3.1 Phase Locked Loops (PLLs) Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider ...
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... FS6370 achieve a desired input-frequency-to-output-frequency ratio without making both the reference and feedback divider values comparatively large. Generally, very large values are undesirable as they degrade the bandwidth of the PLL, increasing phase jitter and acquisition time. To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal cascaded with the dual-modulus pre-scaler ...
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... Reprogramming of either the control registers or the EEPROM is permitted at any time if the MODE pin is a logic-low. Note, however, that a logic-high state on the MODE pin is latched so that only one transfer of EEPROM data to the FS6370 control registers can occur second transfer of EEPROM data into the FS6370 is desired, power (VDD) must be removed and reapplied to the device ...
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... Run Mode If the MODE pin is set to a logic-high, the device enters the run mode. The high state is latched (see MODE pin). The FS6370 then copies the stored EEPROM data into its control registers and begins normal operation based on that data when the self-load is complete ...
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... Programming Migration Path If the design can support I C programming overhead, a cost reduction from the EEPROM-based FS6370 to the register-based FS6377 2 is possible. Figure 5 shows the five pins that may not be compatible between the various devices if programming of the FS6370 or the FS6377 is desired Rev ...
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... Non-Programming Migration Path If the design has solidified on a particular EEPROM programming pattern, the EEPROM pattern can be hard-coded into a ROM-based device. For high-volume requirements, a ROM-based device offers significant cost savings over the FS6370. Contact an ON Semiconductor sales representative for more detail. ...
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... I C-bus commands. 2 8.2.1. Device Address After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W bit. The device address of the FS6370 is Any one of eight possible addresses are available for the EEPROM. The least significant three bits are don’t care’s. ...
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... FS6370 Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word ...
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... FS6370 Figure 6: Random Register Write Procedure Figure 7: Random Register Read Procedure Figure 8: Sequential Register Write Procedure Figure 9: Sequential Register Read Procedure Rev Page www.onsemi.com ...
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... However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output. 9.1.1. Power-Down All power-down functions are controlled by enable bits. That is, the bits select which portions of the FS6370 to power-down when the PD input is asserted. If the power-down bit contains a one, the related circuit will shut down if the PD pin is high (run mode only). When the PD pin is low, power is enabled to all circuits ...
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... FS6370 Table 4: Power-Down Bits Name PDPLL_A (Bit 21) PDPLL_B (Bit 45) PDPLL_C (Bit 69) Reserved (0) (Bit 69) PDPOST_A (Bit 120) PDPOST_B (Bit 121) PDPOSTC (Bit 122) PDPOSTD (Bit 123) Table 5: Divider Control Bits Name REFDIV_A[7:0] (Bits 7-0) REFDIV_B[7:0] (Bits 31-24) REFDIV_C1[7:0] (Bits 55-48) REFDIV_C2[7:0] (Bits 79-72) ...
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... FS6370 Table 6: Post Divider Control Bits Name Description POST_A[3:0] POST divider A (see Table 7) (Bits 99-96) POST_B[3:0] POST divider B (see Table 7) (Bits 103-100) POST_C1[3:0] POST divider C1 (see Table 7) (Bits 107-104) selected when the SEL_CD pin = 0 POST_C2[3:0] POST divider C2 (see Table 7) (Bits 115-112) ...
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... FS6370 Table 8: PLL Tuning Bits Name LFTC_A (Bit 20) LFTC_B (Bit 44) LFTC_C1 (Bit 68) LFTC_C2 (Bit 92) CP_A (Bit 19) CP_B (Bit 43) CP_C1 (Bit 67) CP_C2 (Bit 91) Description Loop Filter Time Constant A Bit = 0 Bit = 1 Loop Filter Time Constant B Bit = 0 Bit = 1 Loop Filter Time Constant C1 - Selected when the SEL_CD pin = 0 ...
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... FS6370 Table 9: MUX Select Bits Name Description MUX A Frequency Select Bit 23 0 MUX_A[1:0] 0 (Bits 23-22 MUX B Frequency Select Bit 47 0 MUX_B[1:0] (Bits 47-46 MUX C1 Frequency Select – Selected when the SEL_CD pin = 0 Bit 71 0 MUX_C1[1:0] (Bits 71-70 MUX C2 Frequency Select – Selected when the SEL_CD pin = 1 ...
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... FS6370 10.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Supply Voltage ground) SS Input Voltage, dc Output Voltage, dc Input Clamp Current < > Output Clamp Current < > Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Re-Flow Solder Profile Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device ...
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... FS6370 Table 12: DC Electrical Specifications Parameter Overall Supply Current, Dynamic Supply Current, Write Supply Current, Read Supply Current, Static Dual Function I/O (P High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) ...
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... FS6370 Table 12: DC Electrical Specifications (Continued) Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Output (XOUT) High-Level Output Source Current Low-Level Output Sink Current Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) ...
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... FS6370 Figure 11: Dynamic Current vs. Output Frequency Rev Page www.onsemi.com ...
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... FS6370 Table 13: AC Timing Specifications Parameter Overall EEPROM Write Cycle Time Output Frequency * VCO Frequency * VCO Gain * Loop Filter Time Constant * Rise Time * Fall Time * Tristate Enable Delay * Tristate Disable Delay * Clock Stabilization Time * Divider Modulus Feedback Divider N F Reference Divider ...
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... FS6370 Table 13: AC Timing Specifications (Continued) Parameter Clock Output (PLL C clock via CLK_C pin) Duty Cycle* T Jitter, Long Term (σ (τ))* j(LT) y Jitter, Period (peak-peak)* t j(ΔP) Clock Output (Crystal Oscillator via CLK_D pin) Duty Cycle* T Jitter, Long Term (σ (τ))* ...
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... FS6370 Figure 12: Bus Timing Data Figure 13: Data Transfer Sequence Rev Page www.onsemi.com ...
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... SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk 12.0 Ordering Information Part Number Package 16-pin (0.150”) SOIC FS6370-01G-XTD (green, ROHS or lead free packaging) 16-pin (0.150”) SOIC FS6370-01G-XTP (green, ROHS or lead free packaging) 8° Symbol Conditions/Description Θ ...
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... Demo Program Operation Launch the fs6370.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear stating: "This version of the demo program cannot communicate with the FS6370 hardware when running on a Windows NT operating system. Do you want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only ...
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... FS6370 13.3.1. Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3 ...
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... FS6370 Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output ...
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... FS6370 14.0 Revision History Revision Date Modification ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...