74HCT9046AN,112 NXP Semiconductors, 74HCT9046AN,112 Datasheet - Page 7

• Manufacturer Part Number: 74HCT9046AN,112
• Description: IC PLL W/BAND GAP VCO 16-DIP
• Manufacturer: NXP Semiconductors
• Type: Phase Lock Loop (PLL)r
• Series: 74HCTr

Specifications of 74HCT9046AN,112

• Number Of Circuits: 1
• Package / Case: 16-DIP (0.300", 7.62mm)
• Pll: Yes
• Input: Clock
• Output: Clock
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 16MHz
• Divider/multiplier: No/No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Frequency-max: 16MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 4.5 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2913-5; 935044170112

NXP Semiconductors
74HCT9046A_6
Product data sheet
8.3.1 Phase Comparator 1 (PC1)
8.2 VCO
8.3 Phase comparators
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one
external resistor R1 (between pins R1 and GND) or two external resistors R1 and R2
(between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine
the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset
if required (see
The high input impedance of the VCO simplifies the design of the low-pass filters by giving
the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. The
DEM_OUT voltage equals that of the VCO input. If DEM_OUT is used, a series resistor
(R
left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator
input (pin COMP_IN), or connected via a frequency divider. The output signal has a duty
cycle of 50 % (maximum expected deviation 1 %), if the VCO input is held at a constant
DC level. A LOW-level at the inhibit input (pin INH) enables the VCO and demodulator,
while a HIGH-level turns both off to minimize standby power consumption.
The signal input (pin SIG_IN) can be directly coupled to the self-biasing amplifier at
pin SIG_IN, provided that the signal swing is between the standard HC family input logic
levels. Capacitive coupling is required for signals with smaller swings.
This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies
(f
characteristic of PC1, assuming ripple (f
where:
The phase comparator gain is:
The average output voltage from PC1, fed to the VCO input via the low-pass filter and
seen at the demodulator output at pin DEM_OUT (V
differences of signals (SIG_IN) and the comparator input (COMP_IN) as shown in
Figure
SIG_IN and with this input the VCO oscillates at the center frequency (f
V
i
•
) must have a 50 % duty cycle to obtain the maximum locking range. The transfer
DEM _OUT
V
V
s
) should be connected from pin DEM_OUT to GND; if unused, DEM_OUT should be
DEM_OUT
DEM_OUT
The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input
(pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For
the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to
minimize standby power consumption.
6. The average of V
=
is the demodulator output at pin DEM_OUT
= V
V
----------
Figure
CC
PC1_OUT
Rev. 06 — 15 September 2009
SIG_IN
4).
(via low-pass)
DEM_OUT
–
K
COMP_IN
p
=
is equal to 0.5V
V
---------- V r
CC
r
= 2f
i
) is suppressed, is:
DEM_OUT
CC
PLL with band gap controlled VCO
when there is no signal or noise at
), is the resultant of the phase
74HCT9046A
© NXP B.V. 2009. All rights reserved.
0
). Typical
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