IDT5T9821NLI IDT, Integrated Device Technology Inc, IDT5T9821NLI Datasheet - Page 34

• Manufacturer Part Number: IDT5T9821NLI
• Description: IC CLK DRIVER ZD PLL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of IDT5T9821NLI

• Pll: Yes with Bypass
• Input: eHSTL, HSTL, LVPECL, LVTTL
• Output: eHSTL, HSTL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5T9821NLI

PROGRAMMING NOTES
PLL configuration. If there is a valif REF and FB input clock connected to the device, and it does not achieve lock, the user should issue a ProgRead instruction
to confirm that the PLL configuration data is valid.
The PLL will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. If the outputs are enabled by the
nSOE pins, the outputs will toggle at the minimum frequency. If the outputs are disabled by the nSOE pins, and the OMODE pin is set high, the nQ[1:0] and
QFB are stopped HIGH, while QFB is stopped LOW.
NOTE:
t1 = t
t2 = t
t3 = t
t4 = t
t5 = t
t6 = t
JTAG
AC ELECTRICAL CHARACTERISTICS
NOTE:
1. Guaranteed by design.
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
t
Symbol
t
t
t
TCLKHIGH
TCLKFALL
Once the IDT5T9821 has been programmed either with a ProgWrite or ProgRestore instruction, the device will attempt to achieve phase lock using the new
On power-up and before the automatic ProgRestore instruction has completed, the internal programming registers will contain the value of '0' for all bits 95:0.
TCLKLOW
TCLKRISE
t
TCLKLOW
TCLKHIGH
t
t
TCLKFALL
TCLKRISE
TCLK
RSR
RST
RST
RSR
(reset pulse width)
(reset recovery)
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
TCLK
TDI/TMS
TDO
TRST
t3
t5
Min.
100
40
40
—
—
50
50
t1
t4
t
t6
DS
Max.
5
5
t
—
—
—
—
—
TCLK
(1)
(1)
t
DH
Standard JTAG Timing
Units
t2
ns
ns
ns
ns
ns
ns
ns
34
SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pF loading on external output signals.
Symbol
t
DOH
t
t
t
DO
DS
DH
Parameter
Data Output
Data Output Hold
Data Input, t
Data Input, t
(1)
RISE
FALL
t
DO
= 3ns
= 3ns
(1)
INDUSTRIAL TEMPERATURE RANGE
TDO
Min.
—
10
10
0
Max.
20
—
—
—
Units
ns
ns
ns
ns