IDT5T9821NLI IDT, Integrated Device Technology Inc, IDT5T9821NLI Datasheet - Page 6

• Manufacturer Part Number: IDT5T9821NLI
• Description: IC CLK DRIVER ZD PLL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of IDT5T9821NLI

• Pll: Yes with Bypass
• Input: eHSTL, HSTL, LVPECL, LVTTL
• Output: eHSTL, HSTL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5T9821NLI

JTAG/ I
NOTE:
1. Only for EEPROM operation; bit 57 must be set to 0 to enable the PLL for proper EEPROM operation. The EEPROM access times are based on the VCO frequency of the PLL
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
95:62 Reserved Bits. Set bits 95:62 to '0'.
(refer to the EEPROM Operation section).
Bit
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Input interface selection for control pins (REF_SEL, PD, PLL_EN, OMODE nSOE). When bit 61 is ‘1’, the control pins are 2.5V LVTTL. When bit 61 is ‘0’, the
control pins are 1.8V LVTTL.
VCO frequency range. When ‘0’, range is 50MHz-125MHz. When ‘1’, range is 100MHz-250MHz.
Output’s disable state. See corresponding external pin OMODE for Pin Description table.
Positive/Negative edge control. When ‘0’/’1’, the outputs are synchronized with the negative/positive edge of the reference clock.
PLL enable/disable. See corresponding external pin PLL_EN in Pin Description table.
Output disable/enable for 1Q/1Q outputs. See corresponding external pin 1SOE in Pin Description table.
Output disable/enable for 2Q/2Q outputs. See corresponding external pin 2SOE in Pin Description table.
Output disable/enable for 3Q/3Q outputs. See corresponding external pin 3SOE in Pin Description table.
Output disable/enable for 4Q/4Q outputs. See corresponding external pin 4SOE in Pin Description table.
Output disable/enable for 5Q/5Qoutputs. See corresponding external pin 5SOE in Pin Description table.
FB Divide-by-N selection
FB Divide-by-N selection
FB Divide-by-N selection
FB Divide-by-N selection
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5
FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank
FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank
REF0 Input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential
REF0 Input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential
REF1 input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential
REF1 input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential
FB input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential
FB input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential
Divide selection for bank 1
Divide selection for bank 1
Divide selection for bank 1
Divide selection for bank 1
Divide selection for bank 1
Divide selection for bank 2
Divide selection for bank 2
Divide selection for bank 2
Divide selection for bank 2
2
C SERIAL DESCRIPTION
Description
6
(1)
INDUSTRIAL TEMPERATURE RANGE