ICS8633AF-01LFT IDT, Integrated Device Technology Inc, ICS8633AF-01LFT Datasheet - Page 8

• Manufacturer Part Number: ICS8633AF-01LFT
• Description: IC BUFFER ZD 1-3 LVPECL 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of ICS8633AF-01LFT

• Pll: Yes with Bypass
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:3
• Differential - Input:output: Yes/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8633AF-01LFT

T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
8633AF-01
RTT =
ERMINATION FOR
((V
FOUT
F
OH
IGURE
+ V
OL
4A. LVPECL O
) / (V
1
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
Z
o
50
UTPUT
UTPUTS
T
RTT
ERMINATION
50
V
CC
FIN
- 2V
www.idt.com
8
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
1-
FOUT
TO
F
IGURE
-3 D
4B. LVPECL O
IFFERENTIAL
Z
Z
o
o
= 50
= 50
125
84
Z
UTPUT
-
ERO
TO
ICS8633-01
3.3V
-3.3V LVPECL
125
84
T
D
ERMINATION
ELAY
REV. B AUGUST 2, 2010
FIN
B
UFFER