STW81101AT STMicroelectronics, STW81101AT Datasheet
STW81101AT
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STW81101AT Summary of contents
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... MHz-1100 MHz, 1650 MHz-2200 MHz and 3300 MHz-4400 MHz bands. The STW81101 is designed with STMicroelectronics advanced 0.35 µm SiGe process. Rev 4 STW81101 1/53 www.st.com ...
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Contents Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block diagram . ...
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STW81101 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STW81101 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram and pin configuration 1 Block diagram and pin configuration 1.1 Block diagram Figure 1. Block diagram 6/53 STW81101 ...
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STW81101 1.2 Pin configuration Figure 2. Pin connection (top view) VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB Table 1. Pin description Pin No 1 VDD_VCOA 2 VDD_DIV2 3 VDD_OUTBUF 4 OUTBUFP 5 OUTBUFN 6 VDD_DIV4 7 VDD_VCOB 8 VDD_ESD 9 ...
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Block diagram and pin configuration Table 1. Pin description (continued) Pin No 10 ICP 11 REXT 12 VDD_CP 13 TEST1 14 LOCK_DET 15 TEST2 16 REF_CLK 17 VDD_PLL 18 EXTVCO_INN 19 EXTVCO_INP 20 VDD_BUFVCO 21 DBUS_SEL 22 VDD_DBUS 23 EXT_PD ...
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STW81101 2 Electrical specifications 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol AV Analog supply voltage CC DV Digital supply voltage CC T Storage temperature stg Electrical static discharge (1) - HBM ESD - CDM-JEDEC standard - MM ...
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Electrical specifications 2.3 Digital logic levels Table 4. Digital logic levels Symbol Parameter V Low level input voltage il V High level input voltage ih V Schmitt trigger hysteresis hyst V Low level output voltage ol V High level output ...
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STW81101 Table 5. Electrical specifications (continued) Symbol Parameter (4) Spurious VCOs (5) K VCOA sensitivity VCOA (5) K VCOB sensitivity VCOB Maximum temperature ΔT variation for continuous LK (5),(6) lock (5) VCO A pushing (5) VCO B pushing V VCO ...
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Electrical specifications Table 5. Electrical specifications (continued) Symbol Parameter PLL miscellaneous I Current consumption PLL (5), (7) t Lock up time lock 1. In order to achieve best phase noise performance 1 V peak level is suggested. 2. The frequency ...
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STW81101 2.5 Phase noise specification Table 6. Phase noise specification Parameter (1) Phase noise performance Inband phase noise floor – closed loop Normalized inband phase noise floor Inband phase noise floor direct output Inband phase noise floor divider by 2 ...
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Electrical specifications Table 6. Phase noise specification (continued) Parameter VCO A with divider by 2 (1650 MHz-1950 MHz) – open loop Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 ...
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STW81101 3 Typical performance characteristics Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop measurements are done with F properly set. The loop filter configuration is depicted in diagram, and the reference clock signal is at ...
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Typical performance characteristics Figure 7. VCO A (div output) closed loop phase noise at 1.8 GHz (F =200 kHz; F STEP I =2 mA) CP 0.53° rms Figure 9. VCO A (div output) closed loop phase ...
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STW81101 Figure 11. PFD frequency spurs (direct output; F =200 kHz) PFD -75 dBc @200KHz Figure 13. PFD frequency spurs (div output; F =800 kHz) PFD < -92 dBc @800KHz Typical performance characteristics Figure 12. PFD frequency spurs ...
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General description 4 General description Figure 1: Block diagram on page 6 an Integer-N PLL frequency synthesizer. The STW81101 consists of two internal low-noise VCOs with buffer blocks, a divider divider low-noise PFD (phase ...
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STW81101 5 Circuit description 5.1 Reference input stage The reference input stage is shown in F input while the inverter used as the frequency reference buffer is AC coupled. ref Figure 15. Reference frequency input buffer F ref 5.2 Reference ...
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Circuit description 5.4 A and B counters The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler, make it possible to generate output frequencies which are spaced only by the reference frequency divided ...
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STW81101 5.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. ...
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Circuit description Table 7. Current value vs. selection CPSEL2 CPSEL1 Note: The current is output on pin ICP. During VCO auto calibration, the ICP and VCTRL pins are forced to VDD/2 Figure ...
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STW81101 5.8 Voltage controlled oscillators 5.8.1 VCO selection The STW81101 integrates two low-noise VCOs to cover a wide band from: ● 3300 MHz to 4400 MHz (direct output) ● 1650 MHz to 2200 MHz (selecting divider by 2) ● 825 ...
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Circuit description The SERCAL bit should be set each division ratio change. The VCO calibration procedure takes approximately 7 periods of the PFD frequency. The maximum allowed F higher F , follow the steps below: PFD 1. ...
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STW81101 Table 9. VCO B performances vs. amplitude setting (Freq=4.1 GHz) PLL_A[1: 5.9 Output stage The differential output signal of the synthesizer can be selected by software among three different signal paths (Direct, Divider by 2 ...
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Circuit description 5.10 External VCO Buffer Although the main benefits of the STW81101 are the two wideband and low-noise VCOs, the capability to use an external VCO is also provided. The external VCO Buffer is able to manage a signal ...
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STW81101 bus interface 2 The I C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL Data is transmitted from microprocessor to the STW81101 through the 2-wire (SDA and 2 ...
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I C bus interface Figure 21. START and STOP conditions SCL SDA START 6.1.3 Byte format and acknowledge Every byte put on the SDA line must be 8 bits long, and be followed by an acknowledge bit to indicate ...
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STW81101 6.1.5 Single-byte write mode Following a START condition, the master sends a device select code with the RW bit set to 0. The STW81101 sends an acknowledge and waits for the 1-byte internal sub-address that provides access to the ...
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I C bus interface 6.2 Timing specification Figure 23. Data and clock SDA SCL t Table 14. Data and clock timing specifications Symbol cwh t cwl Figure 24. Start and stop SDA SCL 30/53 ...
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STW81101 Table 15. Start and stop timing specifications Symbol t start t stop Figure 25. Ack SDA SCL Table 16. Ack timing specifications Symbol Parameter Clock to data start time Data to clock down stop time ...
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I C bus interface 2 6 registers STW81101 has 6 write-only registers and 1 read-only register. 6.3.1 Write-only registers Table 17 gives a short description of the write-only registers. Table 17. Write-only registers HEX code 0x00 0x01 ...
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STW81101 B_COUNTER MSB b7 b6 B10 B9 B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register) A_COUNTER MSB Bits B[2:0] for B_COUNTER, A_COUNTER value. REF_DIVIDER MSB ...
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I C bus interface and P is the selected prescaler modulus. CALIBRATION MSB b7 b6 INITCAL SERCAL This register controls the VCO calibrator using the following values: INITCAL: for test purposes only; must be set ...
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STW81101 6.4 VCO calibration procedure Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION register bit[6]) is set program the device properly while ensuring VCO calibration, perform the following steps before every channel ...
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SPI digital interface 7 SPI digital interface 7.1 General features The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 3.3 V. The STW81101 IC is programmed by means of a high-speed serial-to-parallel interface with ...
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STW81101 Table 19. SPI data structure (MSB is sent first) MSB Address A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 Table 20. ...
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SPI digital interface 7.3 Bit tables Table 22. Bits at 00h and ST1 Serial interface address = 00h Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] ...
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STW81101 Table 23. Bits at Serial interface address = 01h Bit [23] OUTBUF_CTRL_EN [22] CAL_AUTOSTART_EN VCO calibration auto restart enable (0 = Off On) [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] ...
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SPI digital interface The LO output frequency is programmed by setting the proper values for A, B and R according to the following formula: × ( × OUT R where equals D R and P is ...
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STW81101 8 Application information The STW81101 features three different alternately selectable bands: direct output (3.3 to 4.4 GHz), divided by 2 (1.65 to 2.2 GHz) and divided by 4 (850 to 1100 MHz). To achieve a suitable power level, a ...
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Application information Alternatively, you can combine the two outputs in other ways. A first topology for the direct output (3.3 GHz to 4.4 GHz) is suggested in balun and a matching network to adapt the output Ω ...
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STW81101 Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) Vcc 50 ohm RF OUTP RF OUTN 50 ohm Vcc For differential to single conversion, the 50 to 100 Ω Johanson balun is recommended (3700BL15B100). 8.2 Divided by 2 output If ...
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Application information A first solution to combine the differential outputs is the lumped LC type balun tuned in the 2 GHz band (Figure Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) 50 ohm RF OUTP RF OUTN ...
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STW81101 For differential to single conversion, the 50 to 100 Ω Johanson balun (1600BL15B100) is recommended. 8.3 Divided by 4 output The topology, components, values and considerations output (MATCH_LC_LUMP_1G_DIFF.dsn). As for the previous sections, a solution to ...
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Application information Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) 25 ohm RF OUTP RF OUTN 25 ohm 8.4 Evaluation kit An evaluation kit can be delivered upon request, including the following: ● Evaluation board ● GUI (graphical user interface) ...
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STW81101 9 Application diagrams Figure 36. Typical application diagram VDD 1 1n 22p 10 VDD 1 RF Out VDD 1 VDD 1 1n 22p 10 loop filter Note: 1 See Chapter 8: Application information 2 EXT_PD, ADD2, ADD1 (and ADD0 ...
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Application diagrams Figure 37. Ping-pong architecture diagram Note: 1 See Chapter 8: Application information 2 EXT_PD, ADD2, ADD1 (and ADD0 when the I on the board. 3 Loop filter values are for F 4 For best performance VDD 100 kHz ...
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STW81101 Figure 38. Application diagram with external VCO (LO output from STW81101) Note: See Chapter 8: Application information Figure 39. Application diagram with external VCO (LO output from VCO) Application diagrams for further information on output matching topology. 49/53 ...
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Package mechanical data 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages, which have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on ...
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STW81101 Table 25. Package dimensions Ref ddd Min. Typ. 0.800 0.900 0.020 0.650 0.200 0.180 0.250 4.850 5.000 4.750 2.950 3.100 4.850 5.000 4.750 2.950 ...
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... Ordering information 11 Ordering information Table 26. Order codes Part number STW81101AT STW81101ATR 12 Revision history Table 27. Document revision history Date 06-Mar-2006 16-Jun-2006 13-Aug-2007 04-Feb-2008 52/53 Temp range, ° Revision 1 Initial release. Changed from preliminary data to maturity. 2 Updated Chapter 2: Electrical information and Chapter 9: Application Updated Section 6 ...
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... STW81101 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...