STW81101AT STMicroelectronics, STW81101AT Datasheet - Page 12

• Manufacturer Part Number: STW81101AT
• Description: IC SYNTHESIZER MULTI RF 28VFQFPN
• Manufacturer: STMicroelectronics
• Type: Frequency Synthesizer (RF)r

Specifications of STW81101AT

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: No/No
• Frequency - Max: 4.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 4.4GHz
• Number Of Elements: 1
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical specifications
Table 5.
1. In order to achieve best phase noise performance 1 V peak level is suggested.
2. The frequency step is related to the PFD input frequency as follows:
3. See the relationship between ICP and REXT in
4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
5. Guaranteed by design and characterization.
6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range
7. Frequency jump from 2300 to 2150 MHz; it includes the time required by the VCO calibration procedure (7 F
12/53
PLL miscellaneous
Symbol
- F
- F
- F
BW.
for the VCO covering the desired frequency. Once programmed at the initial temperature T
temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status only if the temperature drift (in
either direction) is within the limit specified by
If higher
calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal).
F
I
t
PLL
lock
PFD
step
step
step
=400 kHz).
= F
= F
= F
Δ
PFD
PFD
PFD
T are required the ”VCO calibration auto-restart“ feature can be enabled, thus allowing to re-start the VCO
Current consumption
Lock up time
Electrical specifications (continued)
/2 for divided by 2 output
/4 for divided by 4 output
for direct output
Parameter
(5), (7)
Input buffer, prescaler, digital
dividers, misc.
25 kHz PLL bandwidth; within
1 ppm of frequency error
Δ
T
Section 5.7: Charge
LK
, provided that the final temperature T
Test conditions
pump.
Min
1
is still inside the nominal range.
0
inside the operating
Typ
150
12
PFD
Max
cycles with
STW81101
Unit
mA
µs