ICS810251AGILF IDT, Integrated Device Technology Inc, ICS810251AGILF Datasheet - Page 11

• Manufacturer Part Number: ICS810251AGILF
• Description: IC VCXO SYNC ETH ATTEN 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Jitter Attenuator, Voltage Controlled Crystal Oscillator (VCXO)r

Specifications of ICS810251AGILF

• Pll: Yes with Bypass
• Input: Clock
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 810251AGILF

ICS810251I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS810251I.
Equations and example calculations are also provided.
1.
The total power dissipation for the ICS810251I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for V
Dynamic Power Dissipation at 25MHz
Total Power Dissipation
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
a multi-layer board, the appropriate value is 92.4°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 5. Thermal Resistance
ICS810251AGI REVISION A JULY 28, 2009
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Power Dissipation.
•
•
•
•
85°C + 0.193W *92.4°C/W = 102.8°C. This is well below the limit of 125°C.
Power (core)
Output Impedance R
Output Current I
Power Dissipation on the R
Power (R
Power (25MHz) = C
Total Power
= Power (core)
= 180.18mW + 10.7mW + 2.4mW
= 193.28mW
The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature
θ
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
JA
A
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
OUT
MAX
) = R
MAX
OUT
= V
OUT
+ Power (R
PD
= V
DD_MAX
OUT
* (I
* Frequency * (V
DD_MAX
Power Dissipation due to Loading 50Ω to V
OUT
θ
JA
OUT
* (I
)
for 16 Lead TSSOP, Forced Convection
2
OUT
per LVCMOS output
= 15Ω * (26.7mA)
DD
/ [2 * (50Ω + R
DD
) + Power (25MHz)
+ I
= 3.3V + 5% = 3.465V, which gives worst case results.
DDA
JA
DD
* Pd_total + T
+ I
)
2
DDO
= 8pF * 25MHz * (3.465V)
OUT
) = 3.465V *(40mA + 7mA + 5mA) = 180.18mW
2
)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.7mA
= 10.7mW per output
θ
JA
92.4°C/W
A
by Velocity
0
11
DD
2
/2
= 2.4mW per output
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
88.0°C/W
1
JA
must be used. Assuming no air flow and
©2009 Integrated Device Technology, Inc.
85.9°C/W
2.5