CY28441ZXC Cypress Semiconductor Corp, CY28441ZXC Datasheet - Page 15

• Manufacturer Part Number: CY28441ZXC
• Description: IC CLOCK GEN ALVISO 56-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28441ZXC

• Pll: Yes with Bypass
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 9:18
• Differential - Input:output: No/Yes
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP II
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07679 Rev. **
AC Electrical Specifications
Crystal
T
T
T
T
L
CPU at 0.7V
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
∆T
∆T
V
V
V
V
V
V
SRC
T
T
T
T
T
DC
PERIOD
R
CCJ
ACC
DC
PERIOD
PERIOD
PERIODSS
PERIODSS
PERIODAbs
PERIODAbs
PERIODSSAbs
PERIODSSAbs
CCJ
CCJ2
SKEW
SKEW2
R
RFM
DC
PERIOD
PERIODSS
PERIODAbs
PERIODSSAbs
HIGH
LOW
OX
OVS
UDS
RB
Parameter
R
F
/ T
/ T
F
F
XIN Duty Cycle
XIN Period
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
CPUT and CPUC Duty Cycle
100-MHz CPUT and CPUC Period
133-MHz CPUT and CPUC Period
100-MHz CPUT and CPUC Period, SSC Measured at crossing point V
133-MHz CPUT and CPUC Period, SSC Measured at crossing point V
100-MHz CPUT and CPUC Absolute
Period
133-MHz CPUT and CPUC Absolute
Period
100-MHz CPUT and CPUC Absolute
Period, SSC
133-MHz CPUT and CPUC Absolute
Period, SSC
CPUT/C Cycle to Cycle Jitter
CPU2_ITP Cycle to Cycle Jitter
CPUT to CPUC Clock Skew
CPU2_ITP to CPU0 Clock Skew
CPUT and CPUC Rise and Fall Times
Rise/Fall Matching
Rise Time Variation
Fall Time Variation
Voltage High
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
Minimum Undershoot Voltage
Ring Back Voltage
SRCT and SRCC Duty Cycle
100-MHz SRCT and SRCC Period
100-MHz SRCT and SRCC Period, SSC Measured at crossing point V
100-MHz SRCT and SRCC Absolute
Period
100-MHz SRCT and SRCC Absolute
Period, SSC
Description
The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
When XIN is driven from an external
clock source
Measured between 0.3V
As an average over 1-µs duration
Over 150 ms
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured from V
V
Determined as a fraction of
2*(T
Math averages Figure 15
Math averages Figure 15
See Figure 15. Measure SE
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
Measured at crossing point V
OH
R
= 0.525V
– T
F
)/(T
R
Condition
+ T
OL
F
= 0.175 to
)
DD
and 0.7V
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
OX
DD
9.997001
7.497751
9.997001
7.497751
9.912001
7.412751
9.912001
7.412751
9.997001
9.997001
10.12800
9.872001
69.841
–150
Min.
47.5
–0.3
175
660
250
45
45
–
–
–
–
–
–
–
–
–
–
–
–
10.00300
7.502251
10.05327
7.539950
10.08800
7.587251
10.13827
7.624950
10.00300
10.05327
9.872001
10.17827
CY28441
V
Page 15 of 20
Max.
HIGH
52.5
71.0
10.0
500
300
125
125
100
150
700
125
125
850
550
0.3
0.2
55
20
55
–
–
+
Unit
ppm
mV
mV
mV
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
%
%
%
%
V
V
V
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