CY28441ZXC Cypress Semiconductor Corp, CY28441ZXC Datasheet - Page 9

• Manufacturer Part Number: CY28441ZXC
• Description: IC CLOCK GEN ALVISO 56-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28441ZXC

• Pll: Yes with Bypass
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 9:18
• Differential - Input:output: No/Yes
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP II
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07679 Rev. **
.
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the assertion to active outputs is between 2-6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs will be driven HIGH
within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater
than 200 mV.
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ#[A:B] pins is all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ#[A:B] are to be stopped after their
next transition. The final state of all stopped DIF signals is
LOW, both SRCT clock and SRCC clock outputs will not be
driven.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
SRCC(free running)
SRCT(free running)
SRCT(stoppable)
SRCT(stoppable)
CLKREQ#X
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
REF
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform
PD
Figure 4. Power-down Assertion Timing Waveform
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held low on their next
HIGH to LOW transition and differential clocks must held HIGH
or Hi-Zd (depending on the state of the control register drive
mode bit) on the next diff clock# HIGH to LOW transition within
4 clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tristate.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tristate. Note Figure 4 shows
CPUT = 133 MHz and PD drive mode = ‘1’ for all differential
outputs. This diagram and description is applicable to valid
CPU frequencies 100 and 133 MHz. In the event that PD mode
is desired as the initial power-on state, PD must be asserted
HIGH in less than 10 µs after asserting Vtt_PwrGd#.
CY28441
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