CY28441ZXC Cypress Semiconductor Corp, CY28441ZXC Datasheet - Page 2

• Manufacturer Part Number: CY28441ZXC
• Description: IC CLOCK GEN ALVISO 56-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28441ZXC

• Pll: Yes with Bypass
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 9:18
• Differential - Input:output: No/Yes
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP II
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07679 Rev. **
Pin Description
33, 32
54
44, 43, 41, 40 CPUT/C
36, 35
14, 15
12
16
53
39
56, 3, 4, 5
55
8
9
52
46
47
26, 27
24, 25, 22,
23, 19, 20,
17, 18, 31, 30
11
42
1,7
48
21, 28, 34
37
13
45
2,6
51
29
38
10
Pin No.
CLKREQA#,
CLKREQB#,
CPU_STP#
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
DOT96T, DOT96C
FS_A/USB_48
FS_B/TEST_MODE
FS_C/TEST_SEL
IREF
PCI
PCI_STP#
PCIF0/ITP_EN
PCIF1
REF
SCLK
SDATA
SRC4_SATAT,
SRC4_SATAC
SRCT/C
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
Name
I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
O, DIF Differential CPU clock outputs.
O, DIF Selectable differential CPU or SRC clock output.
O, DIF Fixed 96-MHz clock output.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Differential serial reference clocks.
O, SE 33-MHz clocks.
O, SE 33-MHz clock.
O, SE Reference clock. 3.3V 14.318-MHz clock output.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
GND
I, PU
I, PU
I, PU
GND
GND
GND
GND
GND
Type
I/O
I
I
I
I
I
3.3V LVTTL input for enabling assigned SRC clock, active LOW. CLKREQA#
defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable
SRCT/C5. Assignment can be changed via SMBUS register Byte 8.
3.3V LVTTL input for CPU_STP# active LOW.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
Refer to DC Electrical Specifications table for V
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for V
3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled
to greater than 2.0V when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for V
A precision resistor is attached to this pin, which is connected to the internal
current reference.
3.3V LVTTL input for PCI_STP# active LOW.
1 = CPU2_ITP, 0 = SRC7
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for PLL.
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active LOW) assertion, this pin becomes a real-time input for asserting
power-down (active HIGH).
Description
IL_FS
IL_FS
IL_FS
,V
,V
,V
IH_FS
IH_FS
IH_FS
specifications.
specifications.
specifications.
CY28441
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