STW81100AT-1 STMicroelectronics, STW81100AT-1 Datasheet

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STW81100AT-1

Manufacturer Part Number
STW81100AT-1
Description
IC SYNTHESIZER MULTI RF 28VFQFPN
Manufacturer
STMicroelectronics
Type
Frequency Synthesizerr
Datasheet

Specifications of STW81100AT-1

Pll
Yes
Input
Clock, Crystal
Output
Clock, Crystal
Number Of Circuits
1
Ratio - Input:output
3:2
Differential - Input:output
No/No
Frequency - Max
4.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-VFQFN, 28-VFQFPN
Frequency-max
4.4GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
STW81100AT-1
Manufacturer:
STMicroelectronics
Quantity:
10 000
1
2
The STMicroelectronics STW81100 is an integrat-
ed RF synthesizer and voltage controlled oscilla-
December 2005
Integer-N Frequency Synthesizer
Dual differential integrated VCOs with
automatic central frequency calibration:
– Direct Output:
– Internal divider by 2:
– Internal divider by 4:
Fast lock time: 150µs
Dual modulus prescaler (64/65) and 2
programmable counters to achieve a feedback
division ratio from 4096 to 32767.
Programmable reference frequency divider (9
bits)
Phase frequency comparator and charge pump
Programmable charge pump current
Digital Lock Detector
I
address (1100A
3.3V Power Supply
Power down mode
Small size exposed pad VFQFPN28 package
5x5x1.0mm
Process: BICMOS 0.35µm SiGe
2
C bus interface with 3 bit programmable
Features
3300 – 3900 MHz
3800 – 4400 MHz
1650 – 1950 MHz
1900 – 2200 MHz
825 – 975 MHz
950 – 1100 MHz
Description
MULTI-BAND RF FREQUENCY SYNTHESIZER WITH
2
A
1
A
0
)
tors (VCOs).
Showing high performance, high integration, low
power, and multi-band performances, STW81100
is a low cost one chip alternative to discrete PLL
and VCOs solutions.
STW81100 includes an Integer-N frequency syn-
thesizer and two fully integrated VCOs featuring
low phase noise performance and a noise floor of
-153dBc/Hz. The combination of wide frequency
range VCOs (thanks to center-frequency calibra-
tion over 32 sub-bands) and multiple output op-
tions (direct output, divided by 2 or divided by 4)
allows to cover the 825MHz-1100MHz, the
1650MHz-2200MHz and the 3300MHz-4400MHz
bands.
The STW81100 is designed with STMicroelectron-
ics advanced 0.35µm SiGe process.
3
Figure 1. Package
Table 1. Order Codes
Cellular 3G Infrastructure Equipment
Other Wireless Communication Systems
STW81100ATR-1
STW81100AT-1
Applications
Part Number
INTEGRATED VCO
VFQFPN28
VFQFPN28 in Tape & Reel
STW81100
VFQFPN28
Package
Rev. 6
1/29
S

Related parts for STW81100AT-1

STW81100AT-1 Summary of contents

Page 1

... December 2005 STW81100 INTEGRATED VCO Figure 1. Package VFQFPN28 Table 1. Order Codes Part Number STW81100AT-1 STW81100ATR-1 VFQFPN28 in Tape & Reel tors (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81100 is a low cost one chip alternative to discrete PLL and VCOs solutions. ...

Page 2

STW81100 1 Features .............................................................................................................................................1 2 Description .........................................................................................................................................1 3 Applications ........................................................................................................................................1 4 Electrical Characteristcs.....................................................................................................................5 5 Typical Performance Characteristics..................................................................................................9 6 General Description..........................................................................................................................11 7 Circuit Description ............................................................................................................................11 7.1 Reference input stage ............................................................................................................11 7.2 Reference Divider ..................................................................................................................11 7.3 Prescaler ................................................................................................................................11 7.4 A and B ...

Page 3

Figure 2. Block Diagram VDD_OUTBUF 3 VDD_DIV4 6 DIV4 BUF VDD_DIV2 2 DIV4 VDD_BUFVCO 20 19 EXTVCO_INP EXT VCO BUF EXTVCO_INN 18 VDD_VCO1 1 VDD_VCO2 7 VDD_ESD 8 Figure 3. Pin Connections VDD_VCO1 VDD_VCO1 VDD_OUTBUF VDD_OUTBUF OUTBUFP OUTBUFN REF_IN 4 ...

Page 4

STW81100 Table 2. Pin Description Pin No Name 1 VDD_VCO1 2 VDD_DIV2 3 VDD_OUTBUF 4 OUTBUFP 5 OUTBUFN 6 VDD_DIV4 7 VDD_VCO2 8 VDD_ESD 9 VCTRL 10 ICP 11 REXT 12 VDD_CP 13 TEST1 14 LOCK_DET 15 TEST2 16 REF_IN ...

Page 5

Table 3. Absolute Maximum Ratings Symbol AV Analog Supply voltage CC DV Digital Supply voltage CC T Storage temperature stg ESD Electrical Static Discharge 1 - HBM - CDM-JEDEC Standard Note: 1. The maximum rating of the ESD protection circuitry ...

Page 6

STW81100 Table 6. Electrical Characteristcs (continued) Symbol Parameter VCO DIVIDERS N 1 VCO Divider Ratio REFERENCE and PHASE FREQUENCY DETECTOR f Reference input frequency ref Reference input sensitivity f 4 PFD input frequency PFD f 1 step Frequency step CHARGE ...

Page 7

Table 6. Electrical Characteristcs (continued) Symbol Parameter I Current Consumption LOBUF EXTERNAL VCO (Test purpose only) f Frequency range INVCO P Input level Input level INDC I Current Consumption EXTBUF PLL MISCELLANEOUS I Current Consumption PLL t ...

Page 8

STW81100 Table 7. Phase Noise Performance Parameter VCO B Direct (3800MHz-4400MHz) – Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10MHz Phase Noise ...

Page 9

Typical Performance Characteristics The phase noise is measured with the Agilent E5052A Signal Source Analyzer. All the closed-loop mea- surements are done with f PFD of -141dBc/Hz @1KHz offset and -146dBc/Hz @10KHz offset. Figure 4. VCO A (Direct output) ...

Page 10

STW81100 Figure 8. VCO A (Divider by 2 output) closed loop phase noise Figure 9. VCO A (Divider by 4 output) closed loop phase noise 10/29 Figure 10. VCO B (Divider by 2 output) closed loop phase noise Figure 11. ...

Page 11

General Description The block diagram of Figure 2 ger-N PLL frequency synthesizer. The STW81100 consists of 2 internal low-noise VCOs with buffer blocks, a divider divider low-noise PFD (Phase Frequency Detector), a precise ...

Page 12

STW81100 where: – FVCO: output frequency of VCO. – P: modulus of dual modulus prescaler. – B: division ratio of the main counter. – A: division ratio of the swallow counter. – Fref: input reference frequency. – R: division ratio ...

Page 13

Lock Detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is ...

Page 14

STW81100 7.8 Voltage Controlled Oscillators 7.8.1 VCO Selection Within STW81100 two low-noise VCOs are integrated to cover a wide band from 3300MHz to 4400MHz (direct output), from 1650MHz to 2200MHz (selecting divider by 2) and from 825MHz to 1100MHz (select- ...

Page 15

VCO Voltage Amplitude Control The bits A0 and A1 control the voltage swing of the VCO. The following table gives the voltage level ex- pected on the resonator nodes. Table 9. Code A[1: ...

Page 16

STW81100 8.1.4 STOP condition A LOW to HIGH transition of the data bus SDA identifies start while the clock signal SCL is stable in the HIGH state. A STOP condition terminates communications between the STW81100 and the Bus Master. Figure ...

Page 17

Table 10. S 1100A 8.1.8 Multi-byte write mode The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer ...

Page 18

STW81100 Figure 21. Start and Stop SDA SDA SCL SCL Table 14. Symbol T start1,2 T stop1,2 Figure 22. Ack Table 15. Symbol 8 Register STW81100 has 6 write-only registers and 1 read-only ...

Page 19

Table 16. HEX CODE 0x00 0x01 0x02 0x03 0x04 0x05 Table 17. Functional_Mode MSB b7 b6 PD7 PD6 FUNCTIONAL_MODE register is used to select different functional mode for the STW81100 synthesizer according to the following table: Table 18. Decimal value ...

Page 20

STW81100 Table 20. A_COUNTER MSB Bit B0 for B Counter, A Counter value and bit R8 for Reference divider. Table 21. REF_DIVIDER MSB Reference Clock divider ratio R[7:0] (bit R8 in the ...

Page 21

Table 24. READ-ONLY REGISTER MSB b7 b6 ILLEG END CALB LOCK_DET AL_SUBAD0 This register is automatically addressed in the ‘current byte address read mode’. ILLEGAL_SUBADD: gives “1” if the sub-address value is not correct ENDCALB: at “0” means end of ...

Page 22

STW81100 proximately 2dBm output power over the whole band. This topology is intrinsically narrow band, since the LC balun is tuned at a single frequency. If the application requires a different sub-band, the LC combiner could be easily adjusted to ...

Page 23

By using this topology the STW81100 is capable to deliver approximately 0dBm to a 50Ω load with a return loss grater than 10dB over the whole frequency band (3.3 to 4.4GHz). Those results have been achieved on an FR4 substrate ...

Page 24

STW81100 The same recommendation for the SMD components applies also for the divided by 2 output. Another topology suitable to combine the two outputs for the divided by 2 frequencies is represented in Figure 28 . Figure 28. Lumped output ...

Page 25

If the user prefers to use an RF balun it is possible to adopt the same topology depicted in changing the balun and the resistor value ( range is the 1:1 Johanson 900BL15B050. Figure 30. Lumped output matching for the ...

Page 26

STW81100 10 Application diagram Figure 31. Application diagram VDD 1 1n 22p 10µ VDD 1 22n 51 RF Out 10p 10p 22n 51 VDD 1 VDD 1 1n 22p 10µ loop filter Notes: 1. Output matching component values for 2GHz ...

Page 27

Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in ...

Page 28

STW81100 12 Revision History Table 25. Revision History Date Revision March 2005 April 2005 14-July-2005 25-July-2005 7-Oct-2005 16-Dec-2005 28/29 1 First Issue 2 Changed the maturity from Preliminary to Final datasheet. Modified sections (Tables 6, 7). Added ...

Page 29

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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