STW81100AT-1 STMicroelectronics, STW81100AT-1 Datasheet - Page 7

• Manufacturer Part Number: STW81100AT-1
• Description: IC SYNTHESIZER MULTI RF 28VFQFPN
• Manufacturer: STMicroelectronics
• Type: Frequency Synthesizerr

Specifications of STW81100AT-1

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: No/No
• Frequency - Max: 4.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 4.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6. Electrical Characteristcs (continued)
Notes: 1. Frequency step higher than F
Table 7. Phase Noise Performance
EXTERNAL VCO (Test purpose only)
f
V
PLL MISCELLANEOUS
In Band Phase Noise – Closed Loop
Normalized In Band Phase Noise
Floor
In Band Phase Noise Floor
Direct Output
In Band Phase Noise Floor
Divider by 2
In Band Phase Noise Floor
Divider by 4
PLL Integrated Phase Noise with Divider by 2
Integrated Phase Noise (single
sided) 400Hz to 4MHz
Integrated Phase Noise (single
sided) 100Hz to 25MHz
VCO A Direct (3300MHz-3900MHz) – Open Loop
Phase Noise @ 1 KHz
Phase Noise @ 10 KHz
Phase Noise @ 100 KHz
Phase Noise @ 1 MHz
Phase Noise @ 10 MHz
Phase Noise @ 40 MHz
Symbol
INVCO
I
EXTBUF
I
INDC
t
LOBUF
LOCK
I
P
PLL
IN
2. see relationship between ICP and REXT in the Circuit Description section (Charge Pump)
3. PFD frequency leakage (400KHz) and harmonics
4. Guaranteed by design and characterization.
(Only configurations with B>A and f
Current Consumption
Frequency range
Input level
DC Input level
Current Consumption
Current Consumption
Lock up time
Parameter
Parameter
4
OUT
/4096 (i.e. N values less than 4096) can be used but it is not guaranteed the channel contiguity
ICP= 2mA, PLL BW = 50KHz;
including reference clock contribution
ICP = 4mA, f
(N = 10000), PLL BW = 15KHz
PFD
2
1
≤ 10 MHz are allowed)
DIV4 Buff
DIV2 Buff
Direct Output
VCO Internal Buffer
Input Buffer, Prescaler, Digital
Dividers, misc
40 KHz PLL bandwidth; within
1 ppm of frequency error
Test Condition
PFD
Test Condition
= 400KHz
-212+20log(N)+10log(f
-218+20log(N)+10log(f
-224+20log(N)+10log(f
Min
3.3
Min
0
Typ
150
-212
-105
-128
-148
-156
Typ
26
23
37
15
10
-39
-38
-56
-83
2
Max
Max
-102
-125
-145
-153
4.4
+6
-37
-36
-53
-82
PFD
PFD
PFD
STW81100
)
)
)
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Units
Units
GHz
dBm
mA
mA
mA
mA
mA
dBc
dBc
µs
V
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