STW81100AT-1 STMicroelectronics, STW81100AT-1 Datasheet - Page 14

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STW81100AT-1

Manufacturer Part Number
STW81100AT-1
Description
IC SYNTHESIZER MULTI RF 28VFQFPN
Manufacturer
STMicroelectronics
Type
Frequency Synthesizerr
Datasheet

Specifications of STW81100AT-1

Pll
Yes
Input
Clock, Crystal
Output
Clock, Crystal
Number Of Circuits
1
Ratio - Input:output
3:2
Differential - Input:output
No/No
Frequency - Max
4.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-VFQFN, 28-VFQFPN
Frequency-max
4.4GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STW81100AT-1
Manufacturer:
STMicroelectronics
Quantity:
10 000
STW81100
7.8 Voltage Controlled Oscillators
7.8.1 VCO Selection
Within STW81100 two low-noise VCOs are integrated to cover a wide band from 3300MHz to 4400MHz
(direct output), from 1650MHz to 2200MHz (selecting divider by 2) and from 825MHz to 1100MHz (select-
ing divider by 4).
VCO A frequency range 3300MHz-3900MHz
VCO B frequency range 3800MHz-4400MHz
7.8.2 VCO Frequency Calibration
Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to
the resonator. These frequency ranges are intended to cover the wide band of operation and compensate
for process variation on the VCO center frequency.
An automatic selection of the range is performed when the bit SERCAL rises from “0” to “1”. The charge
pump is inhibited and the pins ICP & VCTRL are at VDD/2 volts.
Then the ranges are tested to select the one which with this VCO input voltage is the nearest to the desired
output frequency (Fout = N*Fref/R). When this selection is achieved the signal ENDCALB (which means
End of Calibration) falls to “0”, then the charge pump is enabled again and SERCAL should be reset to “0”
before the next channel step.
The reference clock signal at the REF_IN input terminal must be running before starting the calibration.
The PLL has just to perform fine adjustment around VDD/2 on the loop filter to reach Fout, which enables
a fast settle.
Figure 16. VCO Sub-Bands Frequency Characteristics
The SERCAL bit should be set to “1” at each division ratio change. It should be noted that in order to reset
the autocalibrator State Machine after a power-up, and anyway before the first calibration, the INITCAL bit
should be set to “1” and back to “0” (this operation is automatically performed by the Power On Reset cir-
cuitry). The calibration takes approximately 7 periods of the PFD Frequency.
The maximum allowed f
to perform the calibration process is 1 MHz. Using an higher f
the following
PFD
PFD
procedure should be adopted:
1. Calibrate the VCO at the desired frequency with an f
less than 1 MHz
PFD
2. Set the A, B and R dividers ratio for the desired f
PFD
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