STW81100AT-1 STMicroelectronics, STW81100AT-1 Datasheet - Page 11

• Manufacturer Part Number: STW81100AT-1
• Description: IC SYNTHESIZER MULTI RF 28VFQFPN
• Manufacturer: STMicroelectronics
• Type: Frequency Synthesizerr

Specifications of STW81100AT-1

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: No/No
• Frequency - Max: 4.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN, 28-VFQFPN
• Frequency-max: 4.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
The block diagram of
ger-N PLL frequency synthesizer.
The STW81100 consists of 2 internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a
low-noise PFD (Phase Frequency Detector), a precise charge pump, a 9-bit programmable reference di-
vider, two programmable counters and a dual-modulus prescaler.
The A-counter (6 bits) and B counter (9 bits) counters, in conjunction with the dual modulus prescaler P/
P+1 (64/65), implement an N integer divider, where N = B*P +A.
The division ratio of both reference and VCO dividers is controlled through an I
All devices operate with a power supply of 3.3 V and can be powered down when not in use.
7
7.1 Reference input stage
The reference input stage is shown in
while the inverter used as the frequency reference buffer is AC coupled.
Figure 12. Reference Frequency Input Buffer
7.2 Reference Divider
The 9-bit programmable reference counter allows the input reference frequency to be divided to produce
the input clock to the PFD. The division ratio is programmed through the I
7.3 Prescaler
The dual-modulus prescaler 64/65 takes the CML clock from the VCO buffer and divides it down to a man-
ageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core which division
ratio depends on the state of the modulus input.
7.4 A and B Counters
The A (6 bits) and B (9 bits) counters, in conjunction with the dual modulus prescaler make it possible to
generate output frequencies which are spaced only by the reference frequency divided by the reference
division ratio. Thus, the division ratio and the VCO output frequency are given by these formulas:
N = B x P + A
General Description
Circuit Description
Figure 2
Fref
Fref
shows the different blocks, which have been integrated to achieve an inte-
Figure 12
F
VDD
VDD
VCO
=
. The resistor network feeds a DC bias at the Fref input
(
----------------------------------------- -
B P
⋅
+
R
A
INV
INV
) F
Power Down
Power Down
⋅
ref
BUF
BUF
2
C bus interface.
2
C bus interface.
STW81100
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