PCF8583P/F5,112 NXP Semiconductors, PCF8583P/F5,112 Datasheet - Page 15
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PCF8583P/F5,112
Manufacturer Part Number
PCF8583P/F5,112
Description
IC CLK/CALENDAR 240X8 RAM 8-DIP
Manufacturer
NXP Semiconductors
Type
Clock/Calendar/NVSRAMr
Datasheet
1.PCF8583T5518.pdf
(37 pages)
Specifications of PCF8583P/F5,112
Package / Case
8-DIP (0.300", 7.62mm)
Memory Size
240B
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD
Interface
I²C, 2-Wire Serial
Voltage - Supply
1 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1084-5
935261345112
PCF8583PN
935261345112
PCF8583PN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PCF8583P/F5,112
Manufacturer:
LTC
Quantity:
147
NXP Semiconductors
8. Characteristics of the I
PCF8583
Product data sheet
8.1.1 Bit transfer
8.1.2 Start and stop conditions
8.1.3 System configuration
8.1 Characteristics
The I
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
One data bit is transferred during each clock pulse (see
line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time are interpreted as a control signal.
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see
A device generating a message is a transmitter; a device receiving a message is the
receiver (see
devices which are controlled by the master are the slaves.
Fig 14. Bit transfer
Fig 15. Definition of start and stop conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
Figure
START condition
All information provided in this document is subject to legal disclaimers.
2
SDA
SCL
Figure
C-bus
S
16). The device that controls the message is the master; and the
Rev. 06 — 6 October 2010
15).
data valid
data line
stable;
allowed
change
Clock and calendar with 240 x 8-bit RAM
of data
Figure
STOP condition
14). The data on the SDA
mbc621
P
PCF8583
© NXP B.V. 2010. All rights reserved.
mbc622
SDA
SCL
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