M41T82RM6F STMicroelectronics, M41T82RM6F Datasheet

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Features ■ Ultra-low battery supply current of 365 nA Factory calibrated accuracy ±5 ppm ■ guaranteed after 2 reflows (SOX18) – Much better accuracies achievable using built-in programmable analog and digital calibration circuits ■ 2 5.5 V clock ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M41T82-M41T83 3.12 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M41T82-M41T83 List of figures Figure 1. M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Description 1 Description The M41T8x are low power serial I (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal for the SOX18 package). Eight bytes of the register map (see clock/calendar function and are configured in binary coded decimal ...

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M41T82-M41T83 Figure 1. M41T82 logic diagram 1. Open drain Figure 2. M41T83 logic diagram 1. For QFN16 package only 2. Defaults to 32 KHz on power-up 3. Open drain V BAT FT/RST SDA SCL V SS ...

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Description Table 1. Signal names Symbol (1) XI (1) XO (2) IRQ1/OUT/FT (3) SQW RST FT/RST (2) IRQ2 SDA SCL V BAT ( For SO8 and QFN16 packages only. 2. For SOX18 and QFN16 ...

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M41T82-M41T83 Figure 3. SO8 (M) connections (M41T82) 1. Open drain output Figure 4. QFN16 (QA) connections (M41T83) 1. Open drain output. 2. Defaults to 32 KHz on power-up. Figure 5. SOX18 (MY) connections (M41T83 pins must be tied ...

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Description Figure 6. M41T82 block diagram CRYSTAL SDA SCL BAT V RST / 2.93 V (S), 2.63 V (R), and 2.32 V (Z). RST SO 2. Open drain output. Figure ...

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M41T82-M41T83 Figure 8. M41T83 block diagram CRYSTAL SDA SCL BAT V RST /V SO (2) 1. Open drain output 2.93 V (S), 2.63 V (R), and 2.32 V (Z). RST SO Figure ...

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Operation 2 Operation The M41T8x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 32 bytes contained in the device can then be ...

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M41T82-M41T83 2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi- directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to ...

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Operation 2.1.5 Acknowledge Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave ...

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M41T82-M41T83 2.2 Read mode In this mode the master reads the M41T8x slave after setting the slave address (see Figure 13 on page acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition ...

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Operation Figure 13. Read mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 14. Alternative read mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS 16/61 WORD S ADDRESS (An) SLAVE ...

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M41T82-M41T83 2.3 Write mode In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is shown in Figure 15. placed on the bus and indicates to the addressed device that word address “An” will follow and ...

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Operation 2.4 Data retention and battery switchover (V Once V falls below the switchover voltage (V CC switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life from ...

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M41T82-M41T83 3 Clock operation The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for ...

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Clock operation 3.1 Power-down time-stamp When a power failure occurs, the time/date counters are copied into the buffer/transfer registers and the halt update bit (HT) is automatically set to a "1". The HT bit prevents the normal copying from counters ...

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M41T82-M41T83 Table 2. M41T82 clock/control register map (32 bytes) Addr 00h 0.1 seconds 01h ST 10 seconds 02h 0 10 minutes 03h CB1 CB0 04h 0 0 05h 0 0 06h 0 0 07h 10 years 08h ...

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Clock operation Table 3. Key to 0 ABE AC0-AC6 ACS AF1, AF2 AL2E BL BMB0-BMB4 CB0, CB1 DC0-DC4 DCS RB0-RB2 RPT11-RPT15 RPT21-RPT25 ST TD0, TD1 TE TF WDF 22/61 Table 2: M41T82 clock/control register map (32 bytes) ...

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M41T82-M41T83 Table 4. M41T83 clock/control register map (32 bytes) Addr 00h 0.1 seconds 01h ST 10 seconds 02h 0 10 minutes 03h CB1 CB0 10 hours 04h 05h 0 0 06h ...

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Clock operation Table 5. Key to 0 ABE A1IE, A2IE AC0-AC6 ACS AF1, AF2 AL2E BL BMB0-BMB4 CB0, CB1 DC0-DC4 DCS OUT OFIE OTP RB0-RB2 RPT11-RPT15 RPT21-RPT25 RS0-RS3 SQWE SRAM/ALM2 ST TD0, TD1 TE TF TI/TP TIE ...

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M41T82-M41T83 3.3 Real-time clock accuracy The M41T8x is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the ...

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Clock operation 3.4 Clock calibration The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at 25 °C. The M41T8x design provides ...

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M41T82-M41T83 the digital calibration circuitry uses periodic counter correction which occurs downstream of the 512 Hz divider chain and hence has no effect on the FT pin. Note: 1 The modified pulses are not observable on the frequency test (FT) ...

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Clock operation Table 6. Digital calibration values Calibration value (binary) DC4 – DC0 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 ...

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M41T82-M41T83 3.4.2 Analog calibration (programmable load capacitance) A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. As discussed in test output can be used to determine the amount of ...

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Clock operation Figure 17. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Table 7. Analog calibration values Analog calibration D7 D6 value Addr ACS AC6 (±) (16 pF) 0 ...

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M41T82-M41T83 The on-chip capacitance can be calculated as follows: where ACS is the sign. For example: ● C (12h = x0000000) = 12.5 pF LOAD ● C (12h =11001000) = 3.5 pF (sign is negative) LOAD ● C (12h = ...

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Clock operation Two methods are available for ascertaining how much calibration a given M41T8x may require: ● The first involves setting the clock, letting it run for a month and comparing known accurate reference and recording deviation ...

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M41T82-M41T83 Figure 20. Crystal isolation example 1. Substrate pad should be tied to V 3.5 Setting the alarm clock registers Codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm ...

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Clock operation 3.6 Optional second programmable alarm and user SRAM When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h through 18h provide control for a second programmable alarm which operates ...

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M41T82-M41T83 A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh) but not de- assert the IRQ1/FT/OUT output. The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. Table 9. Watchdog ...

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Clock operation Table 10. Timer control register map Addr D7 0Fh WDF 10h 11h TE 1. Bit positions labeled with 0 should always be written with logic 0. 2. Writing to the timer register will not reset the TF bit ...

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M41T82-M41T83 3.8.2 Timer flag (TF) At the end of a timer countdown, when the timer reloads set to logic '1.' Regardless of the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading. If ...

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Clock operation Table 13. Square wave output frequency RS3 38/61 Square wave bits RS2 RS1 ...

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M41T82-M41T83 3.10 Battery low warning The M41T8x automatically checks the battery each time V clock rolls over at midnight compared to V BAT register 0Fh, is set if the battery voltage is found to be less than V ...

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Clock operation The M41T8x only checks the battery when powered by V while in backup mode. Thus, users are advised that during long periods in backup mode, the battery can drop to a level at which timekeeping may fail or ...

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M41T82-M41T83 The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to 0. The oscillator fail detect circuit funtions during backup mode triggering event occurs to disrupt the oscillator ...

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Clock operation The timer, oscillator fail detect circuit, alarm 1, and watchdog are ORed together as the primary interrupt sources. The frequency test signal, FT, is used to enable a 512 Hz output on the IRQ1/FT/OUT pin for calibrating the ...

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M41T82-M41T83 3.14.2 Backup mode In backup mode, the operation of the output circuit is as shown in Table 16. Priority for IRQ1/FT/OUT pin when operating in backup mode (1) (2) OUT ABE ...

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Clock operation 3.15 FT/RST pin, frequency test and reset output pin (M41T82 only) On the M41T82, the 512 Hz frequency test signal and the reset output share the same pin, FT/RST. When the FT bit (bit 6 of register 08h) ...

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M41T82-M41T83 3.17 OTP bit operation (M41T83 in SOX18 package only) When the OTP (one time programmable) bit is set to a '1,' the value in the internal OTP registers will be transferred to the analog calibration register (12h) and are ...

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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 19. ...

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M41T82-M41T83 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed ...

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DC and AC parameters Table 22. DC characteristics Sym Parameter Operating voltage (S) V Operating voltage (R) CC Operating voltage (Z) I Input leakage current LI I Output leakage current LO I Supply current CC1 I Supply current (standby) CC2 ...

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... C Load capacitance L 1. Externally supplied if using the QFN16 or SO8 package. STMicroelectronics recommends the Citizen CFS- 145 (1 mm) and the KDS DT- mm) for thru-hole, or the KDS DMX-26S (3 mm) or Micro Crystal MS3V-T1R (1 mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see Section 8: References on page 2 ...

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DC and AC parameters Figure 26. Power down/up mode AC waveforms RST SDA, SCL RST Table 25. Power down/up trip points DC characteristics Sym V Reset threshold voltage RST Battery backup switchover V SO Hysteresis ...

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M41T82-M41T83 Figure 27. Bus timing requirement sequence SDA t BUF SCL P Table 26. AC characteristics Sym f SCL clock frequency SCL t Clock low period LOW t Clock high period HIGH t SDA and SCL rise time R t ...

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Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...

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M41T82-M41T83 Figure 28. QFN16 – 16-lead, quad, flat package, no lead body size outline Note: Drawing is not to scale. Table 27. QFN16 – 16-lead, quad, flat package, no lead pack. mech. ...

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Package mechanical data Figure 29. QFN16 – 16-lead, quad, flat package, no lead mm, recommended footprint Note: Dimensions are shown in millimeters (mm). Figure 30. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data Note: Dimensions shown ...

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M41T82-M41T83 Figure 31. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline Note: Drawing is not to scale. Table 28. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, package mech. data Symbol ...

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Package mechanical data Figure 32. SO8 – 8-lead plastic small package outline A2 b Note: Drawing is not to scale. Table 29. SO8 – 8-lead plastic small outline (150 mils body width), package mech. data Symb ...

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M41T82-M41T83 Figure 33. Carrier tape for QFN16, SOX18, and SO8 packages T TOP COVER TAPE K 0 Table 30. Carrier tape dimensions for QFN16, SOX18, and SO8 packages Package 1.50 12.00 1.75 QFN16 +0.10/ ±0.30 ±0.10 –0.00 ...

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Part numbering 7 Part numbering Table 31. Ordering information Example: Device family M41T Device type 82 (SO8 package only) 83 Operating voltage 3. 2. ...

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M41T82-M41T83 8 References Below is a listing of the crystal component suppliers mentioned in this document. ● KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. ● Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. ● Micro Crystal can be contacted ...

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Revision history 9 Revision history Table 32. Document revision history Date Revision 09-Apr-2009 9 05-Jan-2010 10 25-Mar-2010 11 19-Oct-2010 12 60/61 Updated Table 10, 11, 22, Section 3.4.2, Section 3.5, Section Section 3.8.2, Section 3.8.3, Section ...

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... M41T82-M41T83 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...